1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 3flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 4flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 5flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 6 7flavor_dts_file-135F_DK = stm32mp135f-dk.dts 8 9flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 10 $(flavor_dts_file-135F_DK) 11 12flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 13 14flavorlist-cryp-1G = $(flavor_dts_file-157C_ED1) \ 15 $(flavor_dts_file-157C_EV1) 16 17flavorlist-no_cryp = $(flavorlist-no_cryp-512M) 18 19flavorlist-512M = $(flavorlist-cryp-512M) \ 20 $(flavorlist-no_cryp-512M) 21 22flavorlist-1G = $(flavorlist-cryp-1G) 23 24flavorlist-MP15 = $(flavor_dts_file-157A_DK1) \ 25 $(flavor_dts_file-157C_DK2) \ 26 $(flavor_dts_file-157C_ED1) \ 27 $(flavor_dts_file-157C_EV1) 28 29flavorlist-MP13 = $(flavor_dts_file-135F_DK) 30 31ifneq ($(PLATFORM_FLAVOR),) 32ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 33$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 34endif 35CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 36endif 37 38ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 39$(call force,CFG_STM32_CRYP,n) 40endif 41 42ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 43$(call force,CFG_STM32MP13,y) 44endif 45 46ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 47$(call force,CFG_STM32MP15,y) 48endif 49 50# CFG_STM32MP1x switches are exclusive. 51# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 52# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 53ifeq ($(CFG_STM32MP13),y) 54$(call force,CFG_STM32MP15,n) 55else 56$(call force,CFG_STM32MP15,y) 57$(call force,CFG_STM32MP13,n) 58endif 59ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 60$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 61endif 62ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 63$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 64endif 65 66include core/arch/arm/cpu/cortex-a7.mk 67 68$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 69$(call force,CFG_DRIVERS_CLK,y) 70$(call force,CFG_DRIVERS_CLK_FIXED,n) 71$(call force,CFG_GIC,y) 72$(call force,CFG_INIT_CNTVOFF,y) 73$(call force,CFG_PSCI_ARM32,y) 74$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 75$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 76$(call force,CFG_SM_PLATFORM_HANDLER,y) 77$(call force,CFG_STM32_SHARED_IO,y) 78 79CFG_TEE_CORE_NB_CORE ?= 2 80CFG_WITH_PAGER ?= y 81CFG_WITH_LPAE ?= y 82CFG_WITH_SOFTWARE_PRNG ?= y 83CFG_MMAP_REGIONS ?= 23 84CFG_DTB_MAX_SIZE ?= (256 * 1024) 85CFG_CORE_ASLR ?= n 86 87ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 88# Some drivers mandate DT support 89$(call force,CFG_DRIVERS_CLK_DT,n) 90$(call force,CFG_STM32_CRYP,n) 91$(call force,CFG_STM32_GPIO,n) 92$(call force,CFG_STM32_I2C,n) 93$(call force,CFG_STM32_IWDG,n) 94$(call force,CFG_STM32_TAMP,n) 95$(call force,CFG_STPMIC1,n) 96$(call force,CFG_STM32MP1_SCMI_SIP,n) 97$(call force,CFG_SCMI_PTA,n) 98else 99$(call force,CFG_DRIVERS_CLK_DT,y) 100endif 101 102ifeq ($(CFG_STM32MP13),y) 103$(call force,CFG_CORE_RESERVED_SHM,n) 104$(call force,CFG_STM32MP15,n) 105$(call force,CFG_STM32MP_CLK_CORE,y) 106$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 107$(call force,CFG_STM32MP13_CLK,y) 108$(call force,CFG_STM32MP15_CLK,n) 109CFG_STM32MP_OPP_COUNT ?= 2 110else 111$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 112CFG_CORE_RESERVED_SHM ?= y 113$(call force,CFG_STM32MP15,y) 114$(call force,CFG_STM32MP15_CLK,y) 115endif 116 117ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 118CFG_TZDRAM_START ?= 0xde000000 119CFG_DRAM_SIZE ?= 0x20000000 120endif 121 122CFG_DRAM_BASE ?= 0xc0000000 123CFG_DRAM_SIZE ?= 0x40000000 124CFG_TZSRAM_START ?= 0x2ffc0000 125CFG_TZSRAM_SIZE ?= 0x0003f000 126CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 127CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 128ifeq ($(CFG_STM32MP15),y) 129CFG_TZDRAM_START ?= 0xfe000000 130CFG_TZDRAM_SIZE ?= 0x01e00000 131ifeq ($(CFG_CORE_RESERVED_SHM),y) 132CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 133CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 134endif 135else 136CFG_TZDRAM_SIZE ?= 0x02000000 137CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 138endif #CFG_STM32MP15 139 140CFG_STM32_BSEC ?= y 141CFG_STM32_CRYP ?= y 142CFG_STM32_ETZPC ?= y 143CFG_STM32_GPIO ?= y 144CFG_STM32_I2C ?= y 145CFG_STM32_IWDG ?= y 146CFG_STM32_RNG ?= y 147CFG_STM32_RSTCTRL ?= y 148CFG_STM32_TAMP ?= y 149CFG_STM32_UART ?= y 150CFG_STPMIC1 ?= y 151CFG_TZC400 ?= y 152 153ifeq ($(CFG_STPMIC1),y) 154$(call force,CFG_STM32_I2C,y) 155$(call force,CFG_STM32_GPIO,y) 156endif 157 158# if any crypto driver is enabled, enable the crypto-framework layer 159ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 160$(call force,CFG_STM32_CRYPTO_DRIVER,y) 161endif 162 163CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 164$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 165 166CFG_WDT ?= $(CFG_STM32_IWDG) 167 168# Platform specific configuration 169CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 170 171# SiP/OEM service for non-secure world 172CFG_STM32_BSEC_SIP ?= y 173CFG_STM32MP1_SCMI_SIP ?= n 174ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 175$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 176$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 177$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 178endif 179 180# Default enable SCMI PTA support 181CFG_SCMI_PTA ?= y 182ifeq ($(CFG_SCMI_PTA),y) 183$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 184$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 185CFG_SCMI_MSG_SHM_MSG ?= y 186CFG_SCMI_MSG_SMT ?= y 187endif 188 189CFG_SCMI_MSG_DRIVERS ?= n 190ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 191$(call force,CFG_SCMI_MSG_CLOCK,y) 192$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 193CFG_SCMI_MSG_SHM_MSG ?= y 194CFG_SCMI_MSG_SMT ?= y 195CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 196$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 197endif 198 199ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 200CFG_HWRNG_PTA ?= y 201endif 202ifeq ($(CFG_HWRNG_PTA),y) 203$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 204$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 205$(call force,CFG_HWRNG_QUALITY,1024) 206endif 207 208# Provision enough threads to pass xtest 209ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 210ifeq ($(CFG_WITH_PAGER),y) 211CFG_NUM_THREADS ?= 3 212else 213CFG_NUM_THREADS ?= 10 214endif 215endif 216 217# Default enable some test facitilites 218CFG_ENABLE_EMBEDDED_TESTS ?= y 219CFG_WITH_STATS ?= y 220 221# Enable to allow debug 222CFG_STM32_BSEC_WRITE ?= $(CFG_TEE_CORE_DEBUG) 223 224# Default disable some support for pager memory size constraint 225ifeq ($(CFG_WITH_PAGER),y) 226CFG_TEE_CORE_DEBUG ?= n 227CFG_UNWIND ?= n 228CFG_LOCKDEP ?= n 229CFG_TA_BGET_TEST ?= n 230# Default disable early TA compression to support a smaller HEAP size 231CFG_EARLY_TA_COMPRESS ?= n 232CFG_CORE_HEAP_SIZE ?= 49152 233endif 234 235# Non-secure UART and GPIO/pinctrl for the output console 236CFG_WITH_NSEC_GPIOS ?= y 237CFG_WITH_NSEC_UARTS ?= y 238# UART instance used for early console (0 disables early console) 239CFG_STM32_EARLY_CONSOLE_UART ?= 4 240