drivers: stm32_i2c: register a DT_DRIVER_I2C driver

Registers stm32_i2c driver as a DT_DRIVER_I2C driver.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thom

drivers: stm32_i2c: register a DT_DRIVER_I2C driver

Registers stm32_i2c driver as a DT_DRIVER_I2C driver.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: shared_resources: simplify GPIOZ bank pin count

Changes initialization of GPIOZ bank pin count from the DT bank
node now using the GPIO bank driver probing to get and save the
informa

plat-stm32mp1: shared_resources: simplify GPIOZ bank pin count

Changes initialization of GPIOZ bank pin count from the DT bank
node now using the GPIO bank driver probing to get and save the
information rather than service_init() initcall level as prior
this change.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: add regulator_dt_get_supply()

Implements regulator_dt_get_supply() API function for consumer
drivers to get a regulator supply using the driver device DT node
data. The function

drivers: regulator: add regulator_dt_get_supply()

Implements regulator_dt_get_supply() API function for consumer
drivers to get a regulator supply using the driver device DT node
data. The function returns TEE_ERROR_DEFER_DRIVER_INIT when the
target supply exists but is yet not initialized.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: fixed regulator

Implements fixed voltage level regulator driver to register DT
compatible "regulator-fixed" devices into the regulator framework.
These regulators may be enabled/

drivers: regulator: fixed regulator

Implements fixed voltage level regulator driver to register DT
compatible "regulator-fixed" devices into the regulator framework.
These regulators may be enabled/disabled using a GPIO pin in which
cases CFG_DRIVERS_GPIO shall be enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: interrupt: helper function for raise_pi, raise_sgi, set_affinity

Defines helper API functions to call .raise_pi, .raise_sgi and
.set_affinity handlers of a chip controller. Defines API functio

core: interrupt: helper function for raise_pi, raise_sgi, set_affinity

Defines helper API functions to call .raise_pi, .raise_sgi and
.set_affinity handlers of a chip controller. Defines API function
to query support of these handlers in the interrupt controller.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt: helper function interrupt_alloc_add_conf_handler()

Adds interrupt API function interrupt_alloc_add_conf_handler() to
allocate, configure and register an interrupt handler, providing

core: interrupt: helper function interrupt_alloc_add_conf_handler()

Adds interrupt API function interrupt_alloc_add_conf_handler() to
allocate, configure and register an interrupt handler, providing
interrupt type and priority.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: move to interrupt_call_handlers()

Removes itr_handle() in favor to interrupt_call_handlers(). This
changes updates all implemented main interrupt controller drivers that
are the GIC driver,

drivers: move to interrupt_call_handlers()

Removes itr_handle() in favor to interrupt_call_handlers(). This
changes updates all implemented main interrupt controller drivers that
are the GIC driver, the HFIC driver and Atmel SAIC driver.

Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-k3: drivers: Open TRNG firewall for TIFS

On devices with PLATFORM=k3-am62x, there is only one SA2UL instance,
which is being shared between TIFS and OP-TEE.

Blocking access to TRNG from all ot

plat-k3: drivers: Open TRNG firewall for TIFS

On devices with PLATFORM=k3-am62x, there is only one SA2UL instance,
which is being shared between TIFS and OP-TEE.

Blocking access to TRNG from all other entities other than OP-TEE
is causing firewall exception when being accessed by TIFS.

While there are other platforms with only one sa2ul instance, on AM62x
we support low power mode, in which TIFS access TRNG while waking up
from deep sleep. On other devices, use of TRNG by TIFS is limited to
the time till OP-TEE initializes and firewalls it for other entities.

Allow access to TIFS to use SA2UL TRNG along with OP-TEE.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>

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plat-k3: drivers: Fix values for FW_SECURE_ONLY and FW_NON_SECURE

Fix values for permission bits for secure user, secure supervisor,
non-secure user and non-secure supervisor.

0th-7th bits are for

plat-k3: drivers: Fix values for FW_SECURE_ONLY and FW_NON_SECURE

Fix values for permission bits for secure user, secure supervisor,
non-secure user and non-secure supervisor.

0th-7th bits are for secure user/supervisor permissions and
8th-15th bits are for non-secure user/supervisor permission.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>

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ci: rust: remove build workaround

Since [1] there is no need to build without OPTEE_RUST_ENABLE=y. Remove
the temporary fix.

Link: https://github.com/OP-TEE/build/commit/dfc1f8f492f3efbaa9b9a4c64a0

ci: rust: remove build workaround

Since [1] there is no need to build without OPTEE_RUST_ENABLE=y. Remove
the temporary fix.

Link: https://github.com/OP-TEE/build/commit/dfc1f8f492f3efbaa9b9a4c64a0345084dbd851b [1]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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ci: rust: fix "no space left in device" error

Remove the content of /__t before starting the QEMUv8_check_rust job.
This directory contains things we do not need:

# du -s /__t/* | sort -n -r | hea

ci: rust: fix "no space left in device" error

Remove the content of /__t before starting the QEMUv8_check_rust job.
This directory contains things we do not need:

# du -s /__t/* | sort -n -r | head -n 10
8651892 /__t/CodeQL
1246592 /__t/Python
1015800 /__t/go
668520 /__t/PyPy
560996 /__t/node
63188 /__t/Ruby
16 /__t/Java_Temurin-Hotspot_jdk

Deleting these files saves 11G of disk space in the root directory:

$ diff -u df-h_before df-h_after
[...]
Filesystem Size Used Avail Use% Mounted on
-overlay 84G 67G 17G 81% /
+overlay 84G 56G 28G 67% /
tmpfs 64M 0 64M 0% /dev
shm 64M 0 64M 0% /dev/shm
-/dev/root 84G 67G 17G 81% /__w
+/dev/root 84G 56G 28G 67% /__w
tmpfs 1.4G 1.2M 1.4G 1% /run/docker.sock
tmpfs 3.4G 0 3.4G 0% /proc/acpi
tmpfs 3.4G 0 3.4G 0% /proc/scsi

This fixes the "no space left on device" errors that appeared recently
when running the job.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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libutils: fault_mitigation.h: Fix indentation

Indentation with tab instead of space.

Fixes: ce56605a0ede ("core: support fault mitigations in non-threaded code")
Signed-off-by: Alvin Chang <alvinga

libutils: fault_mitigation.h: Fix indentation

Indentation with tab instead of space.

Fixes: ce56605a0ede ("core: support fault mitigations in non-threaded code")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: regulator: include tee extensions

Adds missing header file for TEE extension macro
TEE_ERROR_DEFER_DRIVER_INIT.

Fixes: 6558b5657faf ("drivers: regulator: register to dt_driver")
Acked-by:

drivers: regulator: include tee extensions

Adds missing header file for TEE extension macro
TEE_ERROR_DEFER_DRIVER_INIT.

Fixes: 6558b5657faf ("drivers: regulator: register to dt_driver")
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: DT property regulator-pull-down

Handle pull down mode for regulators which DT node sets property
regulator-pull-down.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed

drivers: regulator: DT property regulator-pull-down

Handle pull down mode for regulators which DT node sets property
regulator-pull-down.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: DT property regulator-always-on

Handle regulator DT bindings property regulator-always-on.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <

drivers: regulator: DT property regulator-always-on

Handle regulator DT bindings property regulator-always-on.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: list supported levels

Adds regulator API function regulator_supported_voltages() to get the
list of the voltage levels supported by the regulator.

Voltage level array is either

drivers: regulator: list supported levels

Adds regulator API function regulator_supported_voltages() to get the
list of the voltage levels supported by the regulator.

Voltage level array is either an array of increasing ordered levels, in
microvolt, or is a triplet [min, max, step] for linear step incremental
levels.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: ns16550: Implement RX related features

Implement ns16550_getchar() and ns16550_have_rx_data() for RX related
serial operations into ns16550 UART driver.

Signed-off-by: Alvin Chang <alvinga

drivers: ns16550: Implement RX related features

Implement ns16550_getchar() and ns16550_have_rx_data() for RX related
serial operations into ns16550 UART driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: ns16550: Implement helper function to get driver info

Implement chip_to_base_and_data() for ns16550 UART driver to get
effective address and private structure.

Signed-off-by: Alvin Chang <

drivers: ns16550: Implement helper function to get driver info

Implement chip_to_base_and_data() for ns16550 UART driver to get
effective address and private structure.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: fix style issues in asm-defines.c

Fixing a few cases of alignment that doesn't match open parenthesis.

Fixes: c02f9fb09df2 ("arm: add auto generated asm-defines.h")
Signed-off-by: Jens W

core: arm: fix style issues in asm-defines.c

Fixing a few cases of alignment that doesn't match open parenthesis.

Fixes: c02f9fb09df2 ("arm: add auto generated asm-defines.h")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: preserve 64bit smccc when possible

Prior to this patch when a FFA_MSG_SEND_DIRECT_REQ_64 was received the
response was sent as FFA_MSG_SEND_DIRECT_RESP_32. While not breaking
with the FF-

core: ffa: preserve 64bit smccc when possible

Prior to this patch when a FFA_MSG_SEND_DIRECT_REQ_64 was received the
response was sent as FFA_MSG_SEND_DIRECT_RESP_32. While not breaking
with the FF-A specification, it's still a bit unexpected and will cause
an error in the FF-A framework driver. So fix this by keeping track of
the SMCCC (SMC Calling Convention) used during the current
FFA_MSG_SEND_DIRECT_REQ and respond with matching SMCCC.

This has no impact on AArch32 mode since only the 32-bit SMCCC is valid
in that case. The greatest impact on AArch64 is that we must be able to
find out the current SMCCC during RPC, this means storing it in struct
thread_core_local to be able to access it in assembly low level
routines.

Support for FFA_MSG_SEND_DIRECT_REQ_64 is also advertised in
FFA_FEATURES.

Fixes: 15da69cff2ca ("core: ffa: Enable handling 64-bit direct messages")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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ci: build sam-sama5d2_xplained

Adds platform sam-sama5d2_xplained to CI build.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

ci: build sam-sama5d27_som1_ek

Adds platform sam-sama5d27_som1_ek to CI build

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>

core: pta: imx: fix typo DEK blob command

The PTA command had the manufacturing protection prefix instead of the
DEK blob prefix.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jero

core: pta: imx: fix typo DEK blob command

The PTA command had the manufacturing protection prefix instead of the
DEK blob prefix.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Fix condition of is_from_user()

RISC-V defines that xPP(previous privilege mode) field of CSR status
indicates the previous privilege level prior to the trap. Since the
encoding of user

core: riscv: Fix condition of is_from_user()

RISC-V defines that xPP(previous privilege mode) field of CSR status
indicates the previous privilege level prior to the trap. Since the
encoding of user mode is 0, we should compare the xPP field with 0 here
to know that the trap is from user mode.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1

Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x6

riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1

Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x600000,
and the number of interrupt sources should be 95.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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