1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <drivers/gpio.h> 12 #include <drivers/pinctrl.h> 13 #include <drivers/stm32_gpio.h> 14 #include <io.h> 15 #include <kernel/dt.h> 16 #include <kernel/boot.h> 17 #include <kernel/panic.h> 18 #include <kernel/spinlock.h> 19 #include <libfdt.h> 20 #include <mm/core_memprot.h> 21 #include <stdbool.h> 22 #include <stm32_util.h> 23 #include <sys/queue.h> 24 #include <trace.h> 25 #include <util.h> 26 27 #ifndef CFG_DRIVERS_GPIO 28 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 29 #endif 30 31 #define GPIO_PIN_MAX 15 32 33 #define GPIO_MODER_OFFSET 0x00 34 #define GPIO_OTYPER_OFFSET 0x04 35 #define GPIO_OSPEEDR_OFFSET 0x08 36 #define GPIO_PUPDR_OFFSET 0x0c 37 #define GPIO_IDR_OFFSET 0x10 38 #define GPIO_ODR_OFFSET 0x14 39 #define GPIO_BSRR_OFFSET 0x18 40 #define GPIO_AFRL_OFFSET 0x20 41 #define GPIO_AFRH_OFFSET 0x24 42 #define GPIO_SECR_OFFSET 0x30 43 44 #define GPIO_ALT_LOWER_LIMIT 0x8 45 46 #define GPIO_MODE_MASK GENMASK_32(1, 0) 47 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 48 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 49 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 50 51 #define DT_GPIO_BANK_SHIFT 12 52 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 53 #define DT_GPIO_PIN_SHIFT 8 54 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 55 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 56 57 #define DT_GPIO_BANK_NAME0 "GPIOA" 58 59 /* 60 * struct stm32_pinctrl_array - Array of pins in a pin control state 61 * @count: Number of cells in @pinctrl 62 * @pinctrl: Pin control configuration 63 */ 64 struct stm32_pinctrl_array { 65 size_t count; 66 struct stm32_pinctrl pinctrl[]; 67 }; 68 69 /** 70 * struct stm32_gpio_bank - GPIO bank instance 71 * 72 * @base: base address of the GPIO controller registers. 73 * @clock: clock identifier. 74 * @gpio_chip: GPIO chip reference for that GPIO bank 75 * @ngpios: number of GPIOs. 76 * @bank_id: Id of the bank. 77 * @lock: lock protecting the GPIO bank access. 78 * @sec_support: True if bank supports pin security protection, otherwise false 79 * @seccfgr: Secure configuration register value. 80 * @link: Link in bank list 81 */ 82 struct stm32_gpio_bank { 83 vaddr_t base; 84 struct clk *clock; 85 struct gpio_chip gpio_chip; 86 unsigned int ngpios; 87 unsigned int bank_id; 88 unsigned int lock; 89 STAILQ_ENTRY(stm32_gpio_bank) link; 90 }; 91 92 static unsigned int gpio_lock; 93 94 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 95 STAILQ_HEAD_INITIALIZER(bank_list); 96 97 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 98 99 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 100 { 101 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 102 } 103 104 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 105 unsigned int gpio_pin) 106 { 107 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 108 enum gpio_level level = GPIO_LEVEL_HIGH; 109 unsigned int reg_offset = 0; 110 unsigned int mode = 0; 111 112 assert(gpio_pin < bank->ngpios); 113 114 if (clk_enable(bank->clock)) 115 panic(); 116 117 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 118 GPIO_MODE_MASK; 119 120 switch (mode) { 121 case GPIO_MODE_INPUT: 122 reg_offset = GPIO_IDR_OFFSET; 123 break; 124 case GPIO_MODE_OUTPUT: 125 reg_offset = GPIO_ODR_OFFSET; 126 break; 127 default: 128 panic(); 129 } 130 131 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 132 level = GPIO_LEVEL_HIGH; 133 else 134 level = GPIO_LEVEL_LOW; 135 136 clk_disable(bank->clock); 137 138 return level; 139 } 140 141 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 142 enum gpio_level level) 143 { 144 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 145 146 assert(gpio_pin < bank->ngpios); 147 148 if (clk_enable(bank->clock)) 149 panic(); 150 151 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 152 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 153 154 if (level == GPIO_LEVEL_HIGH) 155 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 156 else 157 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 158 159 clk_disable(bank->clock); 160 } 161 162 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 163 unsigned int gpio_pin) 164 { 165 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 166 uint32_t mode = 0; 167 168 assert(gpio_pin < bank->ngpios); 169 170 if (clk_enable(bank->clock)) 171 panic(); 172 173 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 174 GPIO_MODE_MASK; 175 176 clk_disable(bank->clock); 177 178 switch (mode) { 179 case GPIO_MODE_INPUT: 180 return GPIO_DIR_IN; 181 case GPIO_MODE_OUTPUT: 182 return GPIO_DIR_OUT; 183 default: 184 panic(); 185 } 186 } 187 188 static void stm32_gpio_set_direction(struct gpio_chip *chip, 189 unsigned int gpio_pin, 190 enum gpio_dir direction) 191 { 192 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 193 uint32_t exceptions = 0; 194 uint32_t mode = 0; 195 196 assert(gpio_pin < bank->ngpios); 197 198 if (direction == GPIO_DIR_IN) 199 mode = GPIO_MODE_INPUT; 200 else 201 mode = GPIO_MODE_OUTPUT; 202 203 if (clk_enable(bank->clock)) 204 panic(); 205 exceptions = cpu_spin_lock_xsave(&gpio_lock); 206 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 207 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 208 SHIFT_U32(mode, gpio_pin << 1)); 209 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 210 clk_disable(bank->clock); 211 } 212 213 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 214 struct gpio *gpio) 215 { 216 assert(is_stm32_gpio_chip(chip)); 217 free(gpio); 218 } 219 220 static const struct gpio_ops stm32_gpio_ops = { 221 .get_direction = stm32_gpio_get_direction, 222 .set_direction = stm32_gpio_set_direction, 223 .get_value = stm32_gpio_get_level, 224 .set_value = stm32_gpio_set_level, 225 .put = stm32_gpio_put_gpio, 226 }; 227 228 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 229 { 230 return chip && chip->ops == &stm32_gpio_ops; 231 } 232 233 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 234 { 235 struct stm32_gpio_bank *bank = NULL; 236 237 STAILQ_FOREACH(bank, &bank_list, link) 238 if (bank_id == bank->bank_id) 239 return bank; 240 241 panic(); 242 } 243 244 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 245 static void __maybe_unused get_gpio_cfg(uint32_t bank_id, uint32_t pin, 246 struct gpio_cfg *cfg) 247 { 248 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 249 250 if (clk_enable(bank->clock)) 251 panic(); 252 253 /* 254 * Save GPIO configuration bits spread over the few bank registers. 255 * 1bit fields are accessed at bit position being the pin index. 256 * 2bit fields are accessed at bit position being twice the pin index. 257 * 4bit fields are accessed at bit position being fourth the pin index 258 * but accessed from 2 32bit registers at incremental addresses. 259 */ 260 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 261 GPIO_MODE_MASK; 262 263 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 264 265 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 266 (pin << 1)) & GPIO_OSPEED_MASK; 267 268 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 269 GPIO_PUPD_PULL_MASK; 270 271 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 272 273 if (pin < GPIO_ALT_LOWER_LIMIT) 274 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 275 (pin << 2)) & GPIO_ALTERNATE_MASK; 276 else 277 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 278 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 279 GPIO_ALTERNATE_MASK; 280 281 clk_disable(bank->clock); 282 } 283 284 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 285 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 286 { 287 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 288 uint32_t exceptions = 0; 289 290 if (clk_enable(bank->clock)) 291 panic(); 292 exceptions = cpu_spin_lock_xsave(&gpio_lock); 293 294 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 295 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 296 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 297 SHIFT_U32(cfg->mode, pin << 1)); 298 299 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 300 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 301 SHIFT_U32(cfg->otype, pin)); 302 303 /* Load GPIO Output Speed confguration, 2bit value */ 304 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 305 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 306 SHIFT_U32(cfg->ospeed, pin << 1)); 307 308 /* Load GPIO pull configuration, 2bit value */ 309 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 310 SHIFT_U32(cfg->pupd, pin << 1)); 311 312 /* Load pin mux Alternate Function configuration, 4bit value */ 313 if (pin < GPIO_ALT_LOWER_LIMIT) { 314 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 315 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 316 SHIFT_U32(cfg->af, pin << 2)); 317 } else { 318 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 319 320 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 321 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 322 SHIFT_U32(cfg->af, shift)); 323 } 324 325 /* Load GPIO Output direction confuguration, 1bit */ 326 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 327 328 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 329 clk_disable(bank->clock); 330 } 331 332 /* Count pins described in the DT node and get related data if possible */ 333 static int get_pinctrl_from_fdt(const void *fdt, int node, 334 struct stm32_pinctrl *pinctrl, size_t count) 335 { 336 const fdt32_t *cuint = NULL; 337 const fdt32_t *slewrate = NULL; 338 int len = 0; 339 uint32_t i = 0; 340 uint32_t speed = GPIO_OSPEED_LOW; 341 uint32_t pull = GPIO_PUPD_NO_PULL; 342 size_t found = 0; 343 344 cuint = fdt_getprop(fdt, node, "pinmux", &len); 345 if (!cuint) 346 return -FDT_ERR_NOTFOUND; 347 348 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 349 if (slewrate) 350 speed = fdt32_to_cpu(*slewrate); 351 352 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 353 pull = GPIO_PUPD_PULL_UP; 354 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 355 pull = GPIO_PUPD_PULL_DOWN; 356 357 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 358 uint32_t pincfg = 0; 359 uint32_t bank = 0; 360 uint32_t pin = 0; 361 uint32_t mode = 0; 362 uint32_t alternate = 0; 363 uint32_t odata = 0; 364 bool opendrain = false; 365 366 pincfg = fdt32_to_cpu(*cuint); 367 cuint++; 368 369 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 370 371 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 372 373 mode = pincfg & DT_GPIO_MODE_MASK; 374 375 switch (mode) { 376 case 0: 377 mode = GPIO_MODE_INPUT; 378 break; 379 case 1: 380 case 2: 381 case 3: 382 case 4: 383 case 5: 384 case 6: 385 case 7: 386 case 8: 387 case 9: 388 case 10: 389 case 11: 390 case 12: 391 case 13: 392 case 14: 393 case 15: 394 case 16: 395 alternate = mode - 1U; 396 mode = GPIO_MODE_ALTERNATE; 397 break; 398 case 17: 399 mode = GPIO_MODE_ANALOG; 400 break; 401 default: 402 mode = GPIO_MODE_OUTPUT; 403 break; 404 } 405 406 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 407 opendrain = true; 408 409 if (fdt_getprop(fdt, node, "output-high", NULL) && 410 mode == GPIO_MODE_INPUT) { 411 mode = GPIO_MODE_OUTPUT; 412 odata = 1; 413 } 414 415 if (fdt_getprop(fdt, node, "output-low", NULL) && 416 mode == GPIO_MODE_INPUT) { 417 mode = GPIO_MODE_OUTPUT; 418 odata = 0; 419 } 420 421 if (found < count) { 422 struct stm32_pinctrl *ref = &pinctrl[found]; 423 424 ref->bank = (uint8_t)bank; 425 ref->pin = (uint8_t)pin; 426 ref->cfg.mode = mode; 427 if (opendrain) 428 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 429 else 430 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 431 ref->cfg.ospeed = speed; 432 ref->cfg.pupd = pull; 433 ref->cfg.od = odata; 434 ref->cfg.af = alternate; 435 } 436 437 found++; 438 } 439 440 return (int)found; 441 } 442 443 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 444 struct gpio **out_gpio) 445 { 446 TEE_Result res = TEE_ERROR_GENERIC; 447 struct stm32_gpio_bank *bank = data; 448 struct gpio *gpio = NULL; 449 unsigned int shift_1b = 0; 450 unsigned int shift_2b = 0; 451 uint32_t exceptions = 0; 452 uint32_t otype = 0; 453 uint32_t pupd = 0; 454 uint32_t mode = 0; 455 456 res = gpio_dt_alloc_pin(pargs, &gpio); 457 if (res) 458 return res; 459 460 if (gpio->pin >= bank->ngpios) { 461 DMSG("Invalid GPIO reference"); 462 free(gpio); 463 return TEE_ERROR_GENERIC; 464 } 465 466 shift_1b = gpio->pin; 467 shift_2b = SHIFT_U32(gpio->pin, 1); 468 469 if (gpio->dt_flags & GPIO_PULL_UP) 470 pupd = GPIO_PUPD_PULL_UP; 471 else if (gpio->dt_flags & GPIO_PULL_DOWN) 472 pupd = GPIO_PUPD_PULL_DOWN; 473 else 474 pupd = GPIO_PUPD_NO_PULL; 475 476 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 477 otype = GPIO_OTYPE_OPEN_DRAIN; 478 else 479 otype = GPIO_OTYPE_PUSH_PULL; 480 481 if (clk_enable(bank->clock)) 482 panic(); 483 exceptions = cpu_spin_lock_xsave(&gpio_lock); 484 485 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 486 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 487 SHIFT_U32(mode, shift_2b)); 488 489 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 490 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 491 SHIFT_U32(otype, shift_1b)); 492 493 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 494 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 495 SHIFT_U32(pupd, shift_2b)); 496 497 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 498 clk_disable(bank->clock); 499 500 gpio->chip = &bank->gpio_chip; 501 502 *out_gpio = gpio; 503 504 return TEE_SUCCESS; 505 } 506 507 /* Get bank ID from bank node property st,bank-name or panic on failure */ 508 static unsigned int dt_get_bank_id(const void *fdt, int node) 509 { 510 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 511 const fdt32_t *cuint = NULL; 512 int len = 0; 513 514 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 515 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 516 if (!cuint || (len != dt_name_len + 1)) 517 panic("Missing/wrong st,bank-name property"); 518 519 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 520 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 521 panic("Wrong st,bank-name property"); 522 523 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 524 } 525 526 /* 527 * Return whether or not the GPIO bank related to a DT node is already 528 * registered in the GPIO bank link. 529 */ 530 static bool bank_is_registered(const void *fdt, int node) 531 { 532 unsigned int bank_id = dt_get_bank_id(fdt, node); 533 struct stm32_gpio_bank *bank = NULL; 534 535 STAILQ_FOREACH(bank, &bank_list, link) 536 if (bank->bank_id == bank_id) 537 return true; 538 539 return false; 540 } 541 542 /* Get GPIO bank information from the DT */ 543 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 544 const void *compat_data __unused, 545 int range_offset, 546 struct stm32_gpio_bank **out_bank) 547 { 548 TEE_Result res = TEE_ERROR_GENERIC; 549 struct stm32_gpio_bank *bank = NULL; 550 const fdt32_t *cuint = NULL; 551 struct io_pa_va pa_va = { }; 552 struct clk *clk = NULL; 553 size_t blen = 0; 554 paddr_t pa = 0; 555 int len = 0; 556 int i = 0; 557 558 assert(out_bank); 559 560 /* Probe deferrable devices first */ 561 res = clk_dt_get_by_index(fdt, node, 0, &clk); 562 if (res) 563 return res; 564 565 bank = calloc(1, sizeof(*bank)); 566 if (!bank) 567 return TEE_ERROR_OUT_OF_MEMORY; 568 569 /* 570 * Do not rely *only* on the "reg" property to get the address, 571 * but consider also the "ranges" translation property 572 */ 573 pa = fdt_reg_base_address(fdt, node); 574 if (pa == DT_INFO_INVALID_REG) 575 panic("missing reg property"); 576 577 pa_va.pa = pa + range_offset; 578 579 blen = fdt_reg_size(fdt, node); 580 if (blen == DT_INFO_INVALID_REG_SIZE) 581 panic("missing reg size property"); 582 583 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 584 bank->base = io_pa_or_va_secure(&pa_va, blen); 585 bank->bank_id = dt_get_bank_id(fdt, node); 586 bank->clock = clk; 587 bank->gpio_chip.ops = &stm32_gpio_ops; 588 589 /* Parse gpio-ranges with its 4 parameters */ 590 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 591 len /= sizeof(*cuint); 592 if (len % 4) 593 panic("wrong gpio-ranges syntax"); 594 595 /* Get the last defined gpio line (offset + nb of pins) */ 596 for (i = 0; i < len / 4; i++) { 597 bank->ngpios = MAX(bank->ngpios, 598 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 599 fdt32_to_cpu(*(cuint + 3)))); 600 cuint += 4; 601 } 602 603 *out_bank = bank; 604 return TEE_SUCCESS; 605 } 606 607 static void set_bank_gpio_non_secure(struct stm32_gpio_bank *bank) 608 { 609 unsigned int pin = 0; 610 611 for (pin = 0; pin <= bank->ngpios; pin++) 612 stm32_gpio_set_secure_cfg(bank->bank_id, pin, false); 613 } 614 615 /* Parse a pinctrl node to register the GPIO banks it describes */ 616 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 617 const void *compat_data) 618 { 619 TEE_Result res = TEE_SUCCESS; 620 const fdt32_t *cuint = NULL; 621 int range_offs = 0; 622 int b_node = 0; 623 int len = 0; 624 625 /* Read the ranges property (for regs memory translation) */ 626 cuint = fdt_getprop(fdt, node, "ranges", &len); 627 if (!cuint) 628 panic("missing ranges property"); 629 630 len /= sizeof(*cuint); 631 if (len == 3) 632 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 633 634 fdt_for_each_subnode(b_node, fdt, node) { 635 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 636 if (cuint) { 637 /* 638 * We found a property "gpio-controller" in the node: 639 * the node is a GPIO bank description, add it to the 640 * bank list. 641 */ 642 struct stm32_gpio_bank *bank = NULL; 643 644 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 645 bank_is_registered(fdt, b_node)) 646 continue; 647 648 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 649 range_offs, &bank); 650 if (res) 651 return res; 652 653 /* Registering a provider should not defer probe */ 654 res = gpio_register_provider(fdt, b_node, 655 stm32_gpio_get_dt, bank); 656 if (res) 657 panic(); 658 659 STAILQ_INSERT_TAIL(&bank_list, bank, link); 660 661 if (IS_ENABLED(CFG_STM32MP13)) 662 set_bank_gpio_non_secure(bank); 663 } else { 664 if (len != -FDT_ERR_NOTFOUND) 665 panic(); 666 } 667 } 668 669 return TEE_SUCCESS; 670 } 671 672 673 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 674 { 675 int node = 0; 676 const fdt32_t *cuint = NULL; 677 678 fdt_for_each_subnode(node, fdt, pinctrl_node) { 679 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 680 continue; 681 682 cuint = fdt_getprop(fdt, node, "reg", NULL); 683 if (!cuint) 684 continue; 685 686 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 687 continue; 688 689 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 690 if (!cuint) 691 panic(); 692 693 return (int)fdt32_to_cpu(*cuint); 694 } 695 696 return -1; 697 } 698 699 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 700 bool secure) 701 { 702 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 703 uint32_t exceptions = 0; 704 705 if (clk_enable(bank->clock)) 706 panic(); 707 exceptions = cpu_spin_lock_xsave(&gpio_lock); 708 709 if (secure) 710 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 711 else 712 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 713 714 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 715 clk_disable(bank->clock); 716 } 717 718 #ifdef CFG_DRIVERS_PINCTRL 719 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 720 { 721 struct stm32_pinctrl_array *ref = conf->priv; 722 struct stm32_pinctrl *p = ref->pinctrl; 723 size_t pin_count = ref->count; 724 size_t n = 0; 725 726 for (n = 0; n < pin_count; n++) 727 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 728 729 return TEE_SUCCESS; 730 } 731 732 static void stm32_pinctrl_conf_free(struct pinconf *conf) 733 { 734 free(conf); 735 } 736 737 static const struct pinctrl_ops stm32_pinctrl_ops = { 738 .conf_apply = stm32_pinctrl_conf_apply, 739 .conf_free = stm32_pinctrl_conf_free, 740 }; 741 742 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 743 744 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 745 unsigned int *bank, unsigned int *pin, 746 unsigned int *count) 747 { 748 size_t conf_index = 0; 749 size_t pin_count = 0; 750 size_t n = 0; 751 752 assert(count); 753 if (!pinctrl) 754 goto out; 755 756 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 757 struct pinconf *pinconf = pinctrl->confs[conf_index]; 758 struct stm32_pinctrl_array *ref = pinconf->priv; 759 760 /* Consider only the stm32_gpio pins */ 761 if (pinconf->ops != &stm32_pinctrl_ops) 762 continue; 763 764 if (bank || pin) { 765 for (n = 0; n < ref->count; n++) { 766 if (bank && pin_count < *count) 767 bank[pin_count] = ref->pinctrl[n].bank; 768 if (pin && pin_count < *count) 769 pin[pin_count] = ref->pinctrl[n].pin; 770 pin_count++; 771 } 772 } else { 773 pin_count += ref->count; 774 } 775 } 776 777 out: 778 *count = pin_count; 779 } 780 781 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 782 { 783 size_t conf_index = 0; 784 785 if (!pinctrl) 786 return; 787 788 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 789 struct pinconf *pinconf = pinctrl->confs[conf_index]; 790 struct stm32_pinctrl_array *ref = pinconf->priv; 791 struct stm32_pinctrl *pc = NULL; 792 size_t n = 0; 793 794 for (n = 0; n < ref->count; n++) { 795 if (pinconf->ops != &stm32_pinctrl_ops) 796 continue; 797 798 pc = ref->pinctrl + n; 799 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 800 } 801 } 802 } 803 804 /* Allocate and return a pinctrl configuration from a DT reference */ 805 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 806 void *data __unused, 807 struct pinconf **out_pinconf) 808 { 809 struct conf { 810 struct pinconf pinconf; 811 struct stm32_pinctrl_array array_ref; 812 } *loc_conf = NULL; 813 struct stm32_pinctrl *pinctrl = NULL; 814 struct pinconf *pinconf = NULL; 815 const void *fdt = NULL; 816 size_t pin_count = 0; 817 int pinctrl_node = 0; 818 int pinmux_node = 0; 819 int count = 0; 820 821 pinctrl_node = pargs->phandle_node; 822 fdt = pargs->fdt; 823 assert(fdt && pinctrl_node); 824 825 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 826 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 827 pin_count += (size_t)count / sizeof(uint32_t); 828 else if (count != -FDT_ERR_NOTFOUND) 829 panic(); 830 } 831 832 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 833 if (!loc_conf) 834 return TEE_ERROR_OUT_OF_MEMORY; 835 836 pinconf = &loc_conf->pinconf; 837 pinconf->ops = &stm32_pinctrl_ops; 838 pinconf->priv = &loc_conf->array_ref; 839 840 loc_conf->array_ref.count = pin_count; 841 pinctrl = loc_conf->array_ref.pinctrl; 842 843 count = 0; 844 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 845 int found = 0; 846 847 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 848 pin_count - count); 849 if (found <= 0 && found > ((int)pin_count - count)) { 850 /* We can't recover from an error here so let's panic */ 851 panic(); 852 } 853 854 count += found; 855 } 856 857 *out_pinconf = pinconf; 858 859 return TEE_SUCCESS; 860 } 861 #endif /*CFG_DRIVERS_PINCTRL*/ 862 863 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 864 const void *compat_data) 865 { 866 TEE_Result res = TEE_ERROR_GENERIC; 867 868 /* Register GPIO banks described in this pin control node */ 869 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 870 if (res) 871 return res; 872 873 #ifdef CFG_DRIVERS_PINCTRL 874 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 875 (void *)compat_data); 876 if (res) 877 return res; 878 #endif 879 880 return TEE_SUCCESS; 881 } 882 883 static const struct dt_device_match stm32_pinctrl_match_table[] = { 884 { .compatible = "st,stm32mp135-pinctrl" }, 885 { .compatible = "st,stm32mp157-pinctrl" }, 886 { .compatible = "st,stm32mp157-z-pinctrl" }, 887 { } 888 }; 889 890 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 891 .name = "stm32_gpio-pinctrl", 892 .type = DT_DRIVER_PINCTRL, 893 .match_table = stm32_pinctrl_match_table, 894 .probe = stm32_pinctrl_probe, 895 }; 896