1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 */ 5 6 #include <compiler.h> 7 #include <console.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/serial.h> 11 #include <drivers/stm32_uart.h> 12 #include <io.h> 13 #include <keep.h> 14 #include <kernel/delay.h> 15 #include <kernel/dt.h> 16 #include <kernel/panic.h> 17 #include <libfdt.h> 18 #include <stm32_util.h> 19 #include <util.h> 20 21 #define UART_REG_CR1 0x00 /* Control register 1 */ 22 #define UART_REG_CR2 0x04 /* Control register 2 */ 23 #define UART_REG_CR3 0x08 /* Control register 3 */ 24 #define UART_REG_BRR 0x0c /* Baud rate register */ 25 #define UART_REG_RQR 0x18 /* Request register */ 26 #define UART_REG_ISR 0x1c /* Interrupt & status reg. */ 27 #define UART_REG_ICR 0x20 /* Interrupt flag clear reg. */ 28 #define UART_REG_RDR 0x24 /* Receive data register */ 29 #define UART_REG_TDR 0x28 /* Transmit data register */ 30 #define UART_REG_PRESC 0x2c /* Prescaler register */ 31 32 #define PUTC_TIMEOUT_US 1000 33 #define FLUSH_TIMEOUT_US 16000 34 35 /* 36 * Uart Interrupt & status register bits 37 * 38 * Bit 5 RXNE: Read data register not empty/RXFIFO not empty 39 * Bit 6 TC: Transmission complete 40 * Bit 7 TXE/TXFNF: Transmit data register empty/TXFIFO not full 41 * Bit 27 TXFE: TXFIFO threshold reached 42 */ 43 #define USART_ISR_RXNE_RXFNE BIT(5) 44 #define USART_ISR_TC BIT(6) 45 #define USART_ISR_TXE_TXFNF BIT(7) 46 #define USART_ISR_TXFE BIT(27) 47 48 static vaddr_t loc_chip_to_base(struct serial_chip *chip) 49 { 50 struct stm32_uart_pdata *pd = NULL; 51 52 pd = container_of(chip, struct stm32_uart_pdata, chip); 53 54 return io_pa_or_va(&pd->base, 1); 55 } 56 57 static void loc_flush(struct serial_chip *chip) 58 { 59 vaddr_t base = loc_chip_to_base(chip); 60 uint64_t timeout = timeout_init_us(FLUSH_TIMEOUT_US); 61 62 while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXFE)) 63 if (timeout_elapsed(timeout)) 64 return; 65 } 66 67 static void loc_putc(struct serial_chip *chip, int ch) 68 { 69 vaddr_t base = loc_chip_to_base(chip); 70 uint64_t timeout = timeout_init_us(PUTC_TIMEOUT_US); 71 72 while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXE_TXFNF)) 73 if (timeout_elapsed(timeout)) 74 return; 75 76 io_write32(base + UART_REG_TDR, ch); 77 } 78 79 static bool loc_have_rx_data(struct serial_chip *chip) 80 { 81 vaddr_t base = loc_chip_to_base(chip); 82 83 return io_read32(base + UART_REG_ISR) & USART_ISR_RXNE_RXFNE; 84 } 85 86 static int loc_getchar(struct serial_chip *chip) 87 { 88 vaddr_t base = loc_chip_to_base(chip); 89 90 while (!loc_have_rx_data(chip)) 91 ; 92 93 return io_read32(base + UART_REG_RDR) & 0xff; 94 } 95 96 static const struct serial_ops stm32_uart_serial_ops = { 97 .flush = loc_flush, 98 .putc = loc_putc, 99 .have_rx_data = loc_have_rx_data, 100 .getchar = loc_getchar, 101 102 }; 103 DECLARE_KEEP_PAGER(stm32_uart_serial_ops); 104 105 void stm32_uart_init(struct stm32_uart_pdata *pd, vaddr_t base) 106 { 107 pd->base.pa = base; 108 pd->chip.ops = &stm32_uart_serial_ops; 109 } 110 111 static void register_secure_uart(struct stm32_uart_pdata *pd) 112 { 113 size_t __maybe_unused n = 0; 114 115 stm32mp_register_secure_periph_iomem(pd->base.pa); 116 #ifdef CFG_DRIVERS_PINCTRL 117 stm32mp_register_secure_pinctrl(pd->pinctrl); 118 if (pd->pinctrl_sleep) 119 stm32mp_register_secure_pinctrl(pd->pinctrl_sleep); 120 121 #else 122 for (n = 0; n < pd->pinctrl_count; n++) 123 stm32mp_register_secure_gpio(pd->pinctrl[n].bank, 124 pd->pinctrl[n].pin); 125 #endif 126 } 127 128 static void register_non_secure_uart(struct stm32_uart_pdata *pd) 129 { 130 size_t __maybe_unused n = 0; 131 132 stm32mp_register_non_secure_periph_iomem(pd->base.pa); 133 #ifdef CFG_DRIVERS_PINCTRL 134 stm32mp_register_non_secure_pinctrl(pd->pinctrl); 135 if (pd->pinctrl_sleep) 136 stm32mp_register_non_secure_pinctrl(pd->pinctrl_sleep); 137 #else 138 for (n = 0; n < pd->pinctrl_count; n++) 139 stm32mp_register_non_secure_gpio(pd->pinctrl[n].bank, 140 pd->pinctrl[n].pin); 141 #endif 142 } 143 144 struct stm32_uart_pdata *stm32_uart_init_from_dt_node(void *fdt, int node) 145 { 146 TEE_Result res = TEE_ERROR_GENERIC; 147 struct stm32_uart_pdata *pd = NULL; 148 struct dt_node_info info = { }; 149 #if !defined(CFG_DRIVERS_PINCTRL) 150 struct stm32_pinctrl *pinctrl_cfg = NULL; 151 int count = 0; 152 #endif 153 154 fdt_fill_device_info(fdt, &info, node); 155 156 if (info.status == DT_STATUS_DISABLED) 157 return NULL; 158 159 assert(info.reg != DT_INFO_INVALID_REG && 160 info.reg_size != DT_INFO_INVALID_REG_SIZE); 161 162 pd = calloc(1, sizeof(*pd)); 163 if (!pd) 164 panic(); 165 166 pd->chip.ops = &stm32_uart_serial_ops; 167 pd->base.pa = info.reg; 168 pd->secure = (info.status == DT_STATUS_OK_SEC); 169 170 res = clk_dt_get_by_index(fdt, node, 0, &pd->clock); 171 if (res) { 172 EMSG("Failed to get clock: %#"PRIx32, res); 173 panic(); 174 } 175 176 res = clk_enable(pd->clock); 177 if (res) 178 panic(); 179 180 assert(cpu_mmu_enabled()); 181 pd->base.va = (vaddr_t)phys_to_virt(pd->base.pa, 182 pd->secure ? MEM_AREA_IO_SEC : 183 MEM_AREA_IO_NSEC, info.reg_size); 184 185 #ifdef CFG_DRIVERS_PINCTRL 186 res = pinctrl_get_state_by_name(fdt, node, "default", &pd->pinctrl); 187 if (res) 188 panic(); 189 190 res = pinctrl_get_state_by_name(fdt, node, "sleep", &pd->pinctrl_sleep); 191 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 192 panic(); 193 194 res = pinctrl_apply_state(pd->pinctrl); 195 if (res) 196 panic(); 197 #else 198 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0); 199 if (count < 0) 200 panic(); 201 202 if (count) { 203 pinctrl_cfg = calloc(count, sizeof(*pinctrl_cfg)); 204 if (!pinctrl_cfg) 205 panic(); 206 207 stm32_pinctrl_fdt_get_pinctrl(fdt, node, pinctrl_cfg, count); 208 stm32_pinctrl_load_active_cfg(pinctrl_cfg, count); 209 } 210 pd->pinctrl = pinctrl_cfg; 211 pd->pinctrl_count = count; 212 #endif 213 214 if (pd->secure) 215 register_secure_uart(pd); 216 else 217 register_non_secure_uart(pd); 218 219 return pd; 220 } 221