1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 */ 5 6 #ifndef DRIVERS_STM32_I2C_H 7 #define DRIVERS_STM32_I2C_H 8 9 #include <drivers/clk.h> 10 #include <drivers/pinctrl.h> 11 #include <drivers/stm32_gpio.h> 12 #include <kernel/dt.h> 13 #include <mm/core_memprot.h> 14 #include <stdbool.h> 15 #include <stdint.h> 16 #include <util.h> 17 #include <types_ext.h> 18 19 /* 20 * I2C specification values as per version 6.0, 4th of April 2014 [1], 21 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 22 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 23 * 24 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 25 */ 26 #define I2C_STANDARD_RATE U(100000) 27 #define I2C_FAST_RATE U(400000) 28 #define I2C_FAST_PLUS_RATE U(1000000) 29 30 /* 31 * Initialization configuration structure for the STM32 I2C bus. 32 * Refer to the SoC Reference Manual for more details on configuration items. 33 * 34 * @dt_status: non-secure/secure status read from DT 35 * @pbase: I2C interface base address 36 * @reg_size: I2C interface register map size 37 * @clock: I2C bus/interface clock 38 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 39 * @own_address1: 7-bit or 10-bit first device own address. 40 * @dual_address_mode: True if enabling Dual-Addressing mode 41 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 42 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 43 * @general_call_mode: True if enbling General-Call mode 44 * @no_stretch_mode: If enabling the No-Stretch mode 45 * @rise_time: SCL clock pin rising time in nanoseconds 46 * @fall_time: SCL clock pin falling time in nanoseconds 47 * @bus_rate: Specifies the I2C clock frequency in Hertz 48 * @analog_filter: True if enabling analog filter 49 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 50 */ 51 struct stm32_i2c_init_s { 52 unsigned int dt_status; 53 paddr_t pbase; 54 size_t reg_size; 55 struct clk *clock; 56 bool addr_mode_10b_not_7b; 57 uint32_t own_address1; 58 bool dual_address_mode; 59 uint32_t own_address2; 60 uint32_t own_address2_masks; 61 bool general_call_mode; 62 bool no_stretch_mode; 63 uint32_t rise_time; 64 uint32_t fall_time; 65 uint32_t bus_rate; 66 bool analog_filter; 67 uint8_t digital_filter_coef; 68 }; 69 70 enum i2c_state_e { 71 I2C_STATE_RESET, /* Not yet initialized */ 72 I2C_STATE_READY, /* Ready for use */ 73 I2C_STATE_BUSY, /* Internal process ongoing */ 74 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 75 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 76 I2C_STATE_SUSPENDED, /* Bus is supended */ 77 }; 78 79 enum i2c_mode_e { 80 I2C_MODE_NONE, /* No active communication */ 81 I2C_MODE_MASTER, /* Communication in Master Mode */ 82 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 83 I2C_MODE_MEM, /* Communication in Memory Mode */ 84 }; 85 86 #define I2C_ERROR_NONE U(0x0) 87 #define I2C_ERROR_BERR BIT(0) 88 #define I2C_ERROR_ARLO BIT(1) 89 #define I2C_ERROR_ACKF BIT(2) 90 #define I2C_ERROR_OVR BIT(3) 91 #define I2C_ERROR_DMA BIT(4) 92 #define I2C_ERROR_TIMEOUT BIT(5) 93 #define I2C_ERROR_SIZE BIT(6) 94 95 /* I2C interface registers state */ 96 struct i2c_cfg { 97 uint32_t timingr; 98 uint32_t oar1; 99 uint32_t oar2; 100 uint32_t cr1; 101 uint32_t cr2; 102 }; 103 104 /* 105 * I2C bus device 106 * @base: I2C SoC registers base address 107 * @reg_size: I2C SoC registers address map size 108 * @dt_status: non-secure/secure status read from DT 109 * @clock: clock ID 110 * @i2c_state: Driver state ID I2C_STATE_* 111 * @i2c_err: Last error code I2C_ERROR_* 112 * @saved_timing: Saved timing value if already computed 113 * @saved_frequency: Saved frequency value if already computed 114 * @sec_cfg: I2C registers configuration storage 115 * Case CFG_DRIVERS_PINCTRL 116 * @pinctrl: Pin control configuration for the I2C bus in active state 117 * @pinctrl_sleep: Pin control configuration for the I2C bus in standby state 118 * Case !CFG_DRIVERS_PINCTRL 119 * @pinctrl: PINCTRLs configuration for the I2C PINs 120 * @pinctrl_count: Number of PINCTRLs elements 121 */ 122 struct i2c_handle_s { 123 struct io_pa_va base; 124 size_t reg_size; 125 unsigned int dt_status; 126 struct clk *clock; 127 enum i2c_state_e i2c_state; 128 uint32_t i2c_err; 129 uint32_t saved_timing; 130 unsigned long saved_frequency; 131 struct i2c_cfg sec_cfg; 132 #ifdef CFG_DRIVERS_PINCTRL 133 struct pinctrl_state *pinctrl; 134 struct pinctrl_state *pinctrl_sleep; 135 #else 136 struct stm32_pinctrl *pinctrl; 137 size_t pinctrl_count; 138 #endif 139 }; 140 141 /* STM32 specific defines */ 142 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */ 143 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */ 144 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */ 145 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */ 146 #define STM32_I2C_DIGITAL_FILTER_MAX U(16) 147 148 #ifdef CFG_DRIVERS_PINCTRL 149 /* 150 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 151 * 152 * @fdt: Reference to DT 153 * @node: Target I2C node in the DT 154 * @init: Output stm32_i2c_init_s structure 155 * @pinctrl_active: Output active I2C pinctrl state 156 * @pinctrl_sleep: Output suspended I2C pinctrl state 157 * Return a TEE_Result compliant value 158 */ 159 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node, 160 struct stm32_i2c_init_s *init, 161 struct pinctrl_state **pinctrl_active, 162 struct pinctrl_state **pinctrl_sleep); 163 #else 164 /* 165 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 166 * 167 * @fdt: Reference to DT 168 * @node: Target I2C node in the DT 169 * @init: Output stm32_i2c_init_s structure 170 * @pinctrl: Reference to output pinctrl array 171 * @pinctrl_count: Input @pinctrl array size, output expected size upon success 172 * Return a TEE_Result compliant value 173 */ 174 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node, 175 struct stm32_i2c_init_s *init, 176 struct stm32_pinctrl **pinctrl, 177 size_t *pinctrl_count); 178 #endif /*CFG_DRIVERS_PINCTRL*/ 179 180 /* 181 * Initialize I2C bus handle from input configuration directives 182 * 183 * @hi2c: Reference to I2C bus handle structure 184 * @init_data: Input stm32_i2c_init_s structure 185 * Return 0 on success else a negative value 186 */ 187 int stm32_i2c_init(struct i2c_handle_s *hi2c, 188 struct stm32_i2c_init_s *init_data); 189 190 /* 191 * Send a memory write request in the I2C bus 192 * 193 * @hi2c: Reference to I2C bus handle structure 194 * @dev_addr: Target device I2C address 195 * @mem_addr: Target device memory address 196 * @mem_addr_size: Byte size of internal memory address 197 * @p_data: Data to be written 198 * @size: Byte size of the data to be written 199 * @timeout_ms: Timeout value in milliseconds 200 * Return 0 on success else a negative value 201 */ 202 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 203 uint32_t mem_addr, uint32_t mem_addr_size, 204 uint8_t *p_data, size_t size, unsigned int timeout_ms); 205 206 /* 207 * Send a memory read request in the I2C bus 208 * 209 * @hi2c: Reference to I2C bus handle structure 210 * @dev_addr: Target device I2C address 211 * @mem_addr: Target device memory address 212 * @mem_addr_size: Byte size of internal memory address 213 * @p_data: Data to be read 214 * @size: Byte size of the data to be read 215 * @timeout_ms: Timeout value in milliseconds 216 * Return 0 on success else a negative value 217 */ 218 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 219 uint32_t mem_addr, uint32_t mem_addr_size, 220 uint8_t *p_data, size_t size, unsigned int timeout_ms); 221 222 /* 223 * Send a data buffer in master mode on the I2C bus 224 * 225 * @hi2c: Reference to I2C bus handle structure 226 * @dev_addr: Target device I2C address 227 * @p_data: Data to be sent 228 * @size: Byte size of the data to be sent 229 * @timeout_ms: Timeout value in milliseconds 230 * Return 0 on success else a negative value 231 */ 232 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 233 uint8_t *p_data, size_t size, 234 unsigned int timeout_ms); 235 236 /* 237 * Receive a data buffer in master mode on the I2C bus 238 * 239 * @hi2c: Reference to I2C bus handle structure 240 * @dev_addr: Target device I2C address 241 * @p_data: Buffer for the received data 242 * @size: Byte size of the data to be received 243 * @timeout_ms: Timeout value in milliseconds 244 * Return 0 on success else a negative value 245 */ 246 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 247 uint8_t *p_data, size_t size, 248 unsigned int timeout_ms); 249 250 /* 251 * Optimized 1 byte read/write function for unpaged sequences. 252 * 8-bit addressing mode / single byte transferred / use default I2C timeout. 253 * Return 0 on success else a negative value 254 */ 255 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 256 unsigned int mem_addr, uint8_t *p_data, 257 bool write); 258 259 /* 260 * Check link with the I2C device 261 * 262 * @hi2c: Reference to I2C bus handle structure 263 * @dev_addr: Target device I2C address 264 * @trials: Number of attempts of I2C request 265 * @timeout_ms: Timeout value in milliseconds for each I2C request 266 * Return 0 on success else a negative value 267 */ 268 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 269 unsigned int trials, unsigned int timeout_ms); 270 271 /* 272 * Suspend I2C bus. 273 * Bus owner is reponsible for calling stm32_i2c_suspend(). 274 * 275 * @hi2c: Reference to I2C bus handle structure 276 */ 277 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 278 279 /* 280 * Resume I2C bus. 281 * Bus owner is reponsible for calling stm32_i2c_resume(). 282 * 283 * @hi2c: Reference to I2C bus handle structure 284 */ 285 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 286 287 /* 288 * Return true if I2C bus is enabled for secure world only, false otherwise 289 */ 290 static inline bool i2c_is_secure(struct i2c_handle_s *hi2c) 291 { 292 return hi2c->dt_status == DT_STATUS_OK_SEC; 293 } 294 295 #endif /* DRIVERS_STM32_I2C_H*/ 296