core: arm32: update core local flags in native_intr_handler

The AArch32 version of the native_intr_handler() macro has until now
called C function without updating the core local flags to indicate

core: arm32: update core local flags in native_intr_handler

The AArch32 version of the native_intr_handler() macro has until now
called C function without updating the core local flags to indicate that
the temporary stack is in use. This can lead to errors with
CFG_CORE_DEBUG_CHECK_STACKS=y so fix this by setting THREAD_CLF_TMP and
THREAD_CLF_FIQ or THREAD_CLF_IRQ as needed.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values.

drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values. This change allows to better fit the sole consumer of this
API function that is the SCMI server implementation. SCMI specification
states that discrete clock rates list shall follow this order.

Update at91_cpu_opp clock driver to ensure it satisfy this constraint.
The SAM platforms that embed this driver (sama7g5) already satisfy this
constraints but only at its DTS level. This change ensures the driver
will always.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: fix use after free in PMIC driver

Fix PMIC regulator levels arrays handling that missed a pointer reset
after the buffer is freed. At runtime, pmic_list_voltages() handler
function us

plat-stm32mp1: fix use after free in PMIC driver

Fix PMIC regulator levels arrays handling that missed a pointer reset
after the buffer is freed. At runtime, pmic_list_voltages() handler
function uses that reference and is expected to allocate back the
buffer in case non-secure world requests voltage enumeration for the
related regulator.

Fixes: a7990eb02b82 ("plat-stm32mp1: set voltage list at pmic driver init")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: apply "-march" and "-mabi" options to assembler

Update platform-aflags-generic to include the -march option. Without
specifying -march, the assembler will enable the C extension by defa

core: riscv: apply "-march" and "-mabi" options to assembler

Update platform-aflags-generic to include the -march option. Without
specifying -march, the assembler will enable the C extension by default
and generate compressed instructions, even if CFG_RISCV_ISA_C=n.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: use configuration options for RISC-V extensions

RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, ena

core: riscv: use configuration options for RISC-V extensions

RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, enable RVC and FPU extension for QEMU virt machine.

Note that the RISC-V FPU for OP-TEE will be introduced later.
Enable FPU to temporarily bypass incompatible soft/hard-fp
linker errors.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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kernel/link.mk: fix missing build number in version string on first build

Fix an issue with the build number in the version string. While at it,
factor out the duplicated code into mk/macros.mk.

Be

kernel/link.mk: fix missing build number in version string on first build

Fix an issue with the build number in the version string. While at it,
factor out the duplicated code into mk/macros.mk.

Before:

$ rm -rf out/
$ make out/arm-plat-vexpress/core/version.o
UPD out/arm-plat-vexpress/core/.buildcount
GEN out/arm-plat-vexpress/core/version.o
cat: out/arm-plat-vexpress/core/.buildcount: No such file or directory

In addition to the error message, note the missing build number after the
hash sign:

$ strings out/arm-plat-vexpress/core/version.o | grep UTC
4.3.0-48-g9c97e7d52 (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) # Wed Aug 14 16:17:07 UTC 2024 arm

After:

$ rm -rf out/
$ make out/arm-plat-vexpress/core/version.o
UPD out/arm-plat-vexpress/core/.buildcount
GEN out/arm-plat-vexpress/core/version.o
$ strings out/arm-plat-vexpress/core/version.o | grep UTC
4.3.0-48-g9c97e7d52-dev (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) #1 Wed Aug 14 16:17:24 UTC 2024 arm

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: boot_clear_memtag(): use core_mmu_for_each_map()

Use core_mmu_for_each_map() in boot_clear_memtag() to iterate over each
memory region and clear memory tags for each matching region.

Pre

core: arm: boot_clear_memtag(): use core_mmu_for_each_map()

Use core_mmu_for_each_map() in boot_clear_memtag() to iterate over each
memory region and clear memory tags for each matching region.

Preparing for future changes where more than one memory region may use
the same memory type.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: mm: add core_mmu_for_each_map()

Add core_mmu_for_each_map() to iterate over all memory regions, struct
tee_mmap_region.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core: mm: add core_mmu_for_each_map()

Add core_mmu_for_each_map() to iterate over all memory regions, struct
tee_mmap_region.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Zeroize unused parameters before thread_return_to_udomain()

Zeroize unused parameters before calling thread_return_to_udomain() to
avoid leaking information to the untrusted domain unin

core: riscv: Zeroize unused parameters before thread_return_to_udomain()

Zeroize unused parameters before calling thread_return_to_udomain() to
avoid leaking information to the untrusted domain unintentionally.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: increase size of abort stack to 4096

To avoid stack overruns with CFG_WITH_PAGER=y and
CFG_CORE_DEBUG_CHECK_STACKS=y increase the abort stack from 3072 to
4096.

Signed-off-by: Jens Wik

core: arm64: increase size of abort stack to 4096

To avoid stack overruns with CFG_WITH_PAGER=y and
CFG_CORE_DEBUG_CHECK_STACKS=y increase the abort stack from 3072 to
4096.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: crypto: hisilicon: add authenc algorithm

Add authenc algorithm for hisilicon SEC driver

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add_phys_mem(): fix mergeable physical memory

The test in add_phys_mem() to see if two physical memory ranges can be
merged only checks for overlapping memory ranges, but consecutive ranges
ar

core: add_phys_mem(): fix mergeable physical memory

The test in add_phys_mem() to see if two physical memory ranges can be
merged only checks for overlapping memory ranges, but consecutive ranges
are not detected even if they can be merged. Fix this by also checking
if the byte after the lowest range matches the beginning of the next
range.

The resulting merged entry might be mergeable with the previous or next
entry, so add checks for that and merge if possible.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: mm: introduce struct memory_map

Introduce struct memory_map to keep track of the array of struct
tee_mmap_region, covering number of used entries and number of allocated
entries.

core_mmap_is

core: mm: introduce struct memory_map

Introduce struct memory_map to keep track of the array of struct
tee_mmap_region, covering number of used entries and number of allocated
entries.

core_mmap_is_end_of_table() and MEM_AREA_END are now unused so remove
them.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: pm: sam: specify suspend/resume hint based on suspend level

The regulators that are used with the sama5d2 platforms can enter
different levels of low power mode. In order to be able to act

drivers: pm: sam: specify suspend/resume hint based on suspend level

The regulators that are used with the sama5d2 platforms can enter
different levels of low power mode. In order to be able to act
accordingly, pass this information through suspend/resume hint.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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kernel: pm: add suspend type hint

When entering suspend type, the suspend level is platform dependent and
can be set to various values depending on these platform. In order to
allow platforms settin

kernel: pm: add suspend type hint

When entering suspend type, the suspend level is platform dependent and
can be set to various values depending on these platform. In order to
allow platforms setting it in a generic way when entering suspend,
reserve some bits in the suspend/resume hint to pass this information.
Driver can then used it in a platform independent way to execute
specific code depending on it.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ffa: handle VM availability messages for SPs

The VM availability messages sent by the hypervisor to an SP should be
forwarded to the SP, if the SP has subscribed for these based on the SP
mani

core: ffa: handle VM availability messages for SPs

The VM availability messages sent by the hypervisor to an SP should be
forwarded to the SP, if the SP has subscribed for these based on the SP
manifest.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: ffa: read S-EL0 SP properties from manifest

So far the properties of S-EL0 SPs have been hardcoded when queried by
FFA_PARTITION_INFO_GET. This was supposed to be a temporary workaround,
so re

core: ffa: read S-EL0 SP properties from manifest

So far the properties of S-EL0 SPs have been hardcoded when queried by
FFA_PARTITION_INFO_GET. This was supposed to be a temporary workaround,
so replace this with reading the properties from the SP's manifest which
is the proper solution.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: arm: kern.ld.S: align .ARM.ex* sections

Make sure that the .ARM.exidx and .ARM.extab sections are 8 byte aligned
to work with CFG_CORE_SANITIZE_KADDRESS=y.

Signed-off-by: Jens Wiklander <jens

core: arm: kern.ld.S: align .ARM.ex* sections

Make sure that the .ARM.exidx and .ARM.extab sections are 8 byte aligned
to work with CFG_CORE_SANITIZE_KADDRESS=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: don't instrument asan functions

Don't instrument the functions used by CFG_CORE_SANITIZE_KADDRESS=y
since it may cause recursive calls together with
CFG_CORE_DEBUG_CHECK_STACKS=y.

Signed-off-

core: don't instrument asan functions

Don't instrument the functions used by CFG_CORE_SANITIZE_KADDRESS=y
since it may cause recursive calls together with
CFG_CORE_DEBUG_CHECK_STACKS=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: core_mmu_arch: fix PPN field extraction from PTE

The upper bits of page table entry may contain other fields
introduced since Priv. ISA spec. v1.11 (20211203), such as PBMT
and N bits,

core: riscv: core_mmu_arch: fix PPN field extraction from PTE

The upper bits of page table entry may contain other fields
introduced since Priv. ISA spec. v1.11 (20211203), such as PBMT
and N bits, thus PPN field should be masked out with PTE_PPN.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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driver: crypto: hisilicon: replace free() and memzero() by free_wipe()

replace free() and memzero() by free_wipe()

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.f

driver: crypto: hisilicon: replace free() and memzero() by free_wipe()

replace free() and memzero() by free_wipe()

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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driver: crypto: hisilicon: delete msg->result which is not used

delete msg->result which is not used

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linar

driver: crypto: hisilicon: delete msg->result which is not used

delete msg->result which is not used

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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driver: crypto: hisilicon: add ECC sign and verify

add ECC sign and verify

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: ele: enable support for i.MX91

Enable ELE driver support for i.MX91.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: imx_mu: enable support for i.MX91

Enable MU driver support for i.MX91

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>