xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 3026afe00f2b3fc1d81d2f2f84f049da75980a41) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate
68
69mx8mn-flavorlist = \
70	mx8mnevk
71
72mx8mp-flavorlist = \
73	mx8mpevk \
74	mx8mp_rsb3720_6g
75
76mx8qm-flavorlist = \
77	mx8qmmek \
78
79mx8qx-flavorlist = \
80	mx8qxpmek \
81	mx8dxmek \
82
83mx8dxl-flavorlist = \
84	mx8dxlevk \
85
86mx8ulp-flavorlist = \
87	mx8ulpevk \
88
89mx93-flavorlist = \
90	mx93evk \
91
92mx95-flavorlist = \
93	mx95evk \
94
95mx91-flavorlist = \
96	mx91evk \
97
98ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
99$(call force,CFG_MX6,y)
100$(call force,CFG_MX6UL,y)
101$(call force,CFG_TEE_CORE_NB_CORE,1)
102$(call force,CFG_TZC380,y)
103include core/arch/arm/cpu/cortex-a7.mk
104else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
105$(call force,CFG_MX6,y)
106$(call force,CFG_MX6ULL,y)
107$(call force,CFG_TEE_CORE_NB_CORE,1)
108$(call force,CFG_TZC380,y)
109$(call force,CFG_IMX_CAAM,n)
110$(call force,CFG_NXP_CAAM,n)
111$(call force,CFG_IMX_DCP,y)
112include core/arch/arm/cpu/cortex-a7.mk
113else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
114$(call force,CFG_MX6,y)
115$(call force,CFG_MX6Q,y)
116$(call force,CFG_TEE_CORE_NB_CORE,4)
117$(call force,CFG_TZC380,y)
118else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
119$(call force,CFG_MX6,y)
120$(call force,CFG_MX6QP,y)
121$(call force,CFG_TEE_CORE_NB_CORE,4)
122else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
123$(call force,CFG_MX6,y)
124$(call force,CFG_MX6D,y)
125$(call force,CFG_TEE_CORE_NB_CORE,2)
126$(call force,CFG_TZC380,y)
127else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
128$(call force,CFG_MX6,y)
129$(call force,CFG_MX6DL,y)
130$(call force,CFG_TEE_CORE_NB_CORE,2)
131$(call force,CFG_TZC380,y)
132else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
133$(call force,CFG_MX6,y)
134$(call force,CFG_MX6S,y)
135$(call force,CFG_TEE_CORE_NB_CORE,1)
136else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
137$(call force,CFG_MX6,y)
138$(call force,CFG_MX6SL,y)
139$(call force,CFG_TEE_CORE_NB_CORE,1)
140$(call force,CFG_IMX_CAAM,n)
141$(call force,CFG_NXP_CAAM,n)
142$(call force,CFG_IMX_DCP,y)
143else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
144$(call force,CFG_MX6,y)
145$(call force,CFG_MX6SLL,y)
146$(call force,CFG_TEE_CORE_NB_CORE,1)
147$(call force,CFG_IMX_CAAM,n)
148$(call force,CFG_NXP_CAAM,n)
149$(call force,CFG_IMX_DCP,y)
150$(call force,CFG_NO_SMP,y)
151else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
152$(call force,CFG_MX6,y)
153$(call force,CFG_MX6SX,y)
154$(call force,CFG_TEE_CORE_NB_CORE,1)
155else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
156$(call force,CFG_MX7,y)
157$(call force,CFG_TEE_CORE_NB_CORE,1)
158include core/arch/arm/cpu/cortex-a7.mk
159else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
160$(call force,CFG_MX7,y)
161$(call force,CFG_TEE_CORE_NB_CORE,2)
162include core/arch/arm/cpu/cortex-a7.mk
163else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
164$(call force,CFG_MX7ULP,y)
165$(call force,CFG_TEE_CORE_NB_CORE,1)
166$(call force,CFG_TZC380,n)
167$(call force,CFG_IMX_CSU,n)
168include core/arch/arm/cpu/cortex-a7.mk
169else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
170$(call force,CFG_MX8MQ,y)
171$(call force,CFG_MX8M,y)
172$(call force,CFG_ARM64_core,y)
173$(call force,CFG_TZC380,y)
174CFG_DRAM_BASE ?= 0x40000000
175CFG_TEE_CORE_NB_CORE ?= 4
176else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
177$(call force,CFG_MX8MM,y)
178$(call force,CFG_MX8M,y)
179$(call force,CFG_ARM64_core,y)
180$(call force,CFG_TZC380,y)
181CFG_DRAM_BASE ?= 0x40000000
182CFG_TEE_CORE_NB_CORE ?= 4
183else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
184$(call force,CFG_MX8MN,y)
185$(call force,CFG_MX8M,y)
186$(call force,CFG_ARM64_core,y)
187$(call force,CFG_TZC380,y)
188CFG_DRAM_BASE ?= 0x40000000
189CFG_TEE_CORE_NB_CORE ?= 4
190else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
191$(call force,CFG_MX8MP,y)
192$(call force,CFG_MX8M,y)
193$(call force,CFG_ARM64_core,y)
194$(call force,CFG_TZC380,y)
195CFG_DRAM_BASE ?= 0x40000000
196CFG_TEE_CORE_NB_CORE ?= 4
197else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
198$(call force,CFG_MX8QM,y)
199$(call force,CFG_ARM64_core,y)
200$(call force,CFG_IMX_SNVS,n)
201CFG_IMX_LPUART ?= y
202CFG_DRAM_BASE ?= 0x80000000
203CFG_TEE_CORE_NB_CORE ?= 6
204$(call force,CFG_IMX_OCOTP,n)
205else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
206$(call force,CFG_MX8QX,y)
207$(call force,CFG_ARM64_core,y)
208$(call force,CFG_IMX_SNVS,n)
209CFG_IMX_LPUART ?= y
210CFG_DRAM_BASE ?= 0x80000000
211CFG_TEE_CORE_NB_CORE ?= 4
212$(call force,CFG_IMX_OCOTP,n)
213else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
214$(call force,CFG_MX8DXL,y)
215$(call force,CFG_ARM64_core,y)
216$(call force,CFG_IMX_SNVS,n)
217CFG_IMX_LPUART ?= y
218CFG_DRAM_BASE ?= 0x80000000
219$(call force,CFG_TEE_CORE_NB_CORE,2)
220$(call force,CFG_IMX_OCOTP,n)
221else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
222$(call force,CFG_MX8ULP,y)
223$(call force,CFG_ARM64_core,y)
224CFG_IMX_LPUART ?= y
225CFG_DRAM_BASE ?= 0x80000000
226CFG_TEE_CORE_NB_CORE ?= 2
227$(call force,CFG_NXP_SNVS,n)
228$(call force,CFG_IMX_OCOTP,n)
229CFG_IMX_MU ?= y
230CFG_IMX_ELE ?= n
231else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx93-flavorlist)))
232$(call force,CFG_MX93,y)
233$(call force,CFG_ARM64_core,y)
234CFG_IMX_LPUART ?= y
235CFG_DRAM_BASE ?= 0x80000000
236CFG_TEE_CORE_NB_CORE ?= 2
237$(call force,CFG_NXP_SNVS,n)
238$(call force,CFG_IMX_OCOTP,n)
239$(call force,CFG_TZC380,n)
240$(call force,CFG_CRYPTO_DRIVER,n)
241$(call force,CFG_NXP_CAAM,n)
242CFG_IMX_MU ?= y
243CFG_IMX_ELE ?= n
244else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx95-flavorlist)))
245$(call force,CFG_MX95,y)
246$(call force,CFG_ARM64_core,y)
247CFG_IMX_LPUART ?= y
248CFG_DRAM_BASE ?= 0x80000000
249CFG_TEE_CORE_NB_CORE ?= 6
250$(call force,CFG_NXP_SNVS,n)
251$(call force,CFG_IMX_OCOTP,n)
252$(call force,CFG_TZC380,n)
253$(call force,CFG_NXP_CAAM,n)
254else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx91-flavorlist)))
255$(call force,CFG_MX91,y)
256$(call force,CFG_ARM64_core,y)
257CFG_IMX_LPUART ?= y
258CFG_DRAM_BASE ?= 0x80000000
259CFG_TEE_CORE_NB_CORE ?= 1
260$(call force,CFG_NXP_SNVS,n)
261$(call force,CFG_IMX_OCOTP,n)
262$(call force,CFG_TZC380,n)
263$(call force,CFG_NXP_CAAM,n)
264CFG_IMX_MU ?= y
265else
266$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
267endif
268
269ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
270CFG_DDR_SIZE ?= 0x40000000
271CFG_NS_ENTRY_ADDR ?= 0x80800000
272CFG_IMX_WDOG_EXT_RESET ?= y
273endif
274
275ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
276CFG_DDR_SIZE ?= 0x40000000
277CFG_UART_BASE ?= UART1_BASE
278CFG_IMX_WDOG_EXT_RESET ?= y
279endif
280
281ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
282CFG_DDR_SIZE ?= 0x20000000
283CFG_NS_ENTRY_ADDR ?= 0x87800000
284CFG_DT_ADDR ?= 0x83100000
285CFG_UART_BASE ?= UART5_BASE
286CFG_BOOT_SECONDARY_REQUEST ?= n
287CFG_EXTERNAL_DTB_OVERLAY ?= y
288CFG_IMX_WDOG_EXT_RESET ?= y
289endif
290
291ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
292CFG_DDR_SIZE ?= 0x20000000
293CFG_NS_ENTRY_ADDR ?= 0x80800000
294CFG_BOOT_SECONDARY_REQUEST ?= n
295endif
296
297ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
298CFG_DDR_SIZE ?= 0x20000000
299CFG_NS_ENTRY_ADDR ?= 0x87800000
300CFG_DT_ADDR ?= 0x83100000
301CFG_BOOT_SECONDARY_REQUEST ?= n
302CFG_EXTERNAL_DTB_OVERLAY = y
303CFG_IMX_WDOG_EXT_RESET = y
304endif
305
306ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
307CFG_DDR_SIZE ?= 0x40000000
308CFG_NS_ENTRY_ADDR ?= 0x60800000
309CFG_UART_BASE ?= UART4_BASE
310endif
311
312ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
313	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
314	mx6dapalis mx6qapalis))
315CFG_DDR_SIZE ?= 0x40000000
316CFG_NS_ENTRY_ADDR ?= 0x12000000
317endif
318
319ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
320	mx6dlsabreauto mx6solosabreauto))
321CFG_DDR_SIZE ?= 0x80000000
322CFG_NS_ENTRY_ADDR ?= 0x12000000
323CFG_UART_BASE ?= UART4_BASE
324endif
325
326ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
327CFG_DDR_SIZE ?= 0x80000000
328CFG_UART_BASE ?= UART1_BASE
329endif
330
331ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
332CFG_DDR_SIZE ?= 0x40000000
333CFG_NS_ENTRY_ADDR ?= 0x12000000
334endif
335
336ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
337CFG_DDR_SIZE ?= 0x40000000
338CFG_NS_ENTRY_ADDR ?= 0x12000000
339CFG_UART_BASE ?= UART2_BASE
340endif
341
342ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
343CFG_NS_ENTRY_ADDR ?= 0x80800000
344CFG_DDR_SIZE ?= 0x40000000
345endif
346
347ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
348CFG_NS_ENTRY_ADDR ?= 0x80800000
349CFG_DDR_SIZE ?= 0x80000000
350endif
351
352ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
353CFG_DDR_SIZE ?= 0x80000000
354CFG_NS_ENTRY_ADDR ?= 0x80800000
355endif
356
357ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
358CFG_DDR_SIZE ?= 0x40000000
359CFG_NS_ENTRY_ADDR ?= 0x80800000
360endif
361
362ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
363CFG_DDR_SIZE ?= 0x40000000
364CFG_UART_BASE ?= UART1_BASE
365endif
366
367ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
368CFG_DDR_SIZE ?= 0x20000000
369CFG_NS_ENTRY_ADDR ?= 0x80800000
370endif
371
372ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
373CFG_DDR_SIZE ?= 0x10000000
374CFG_NS_ENTRY_ADDR ?= 0x80800000
375CFG_UART_BASE ?= UART5_BASE
376endif
377
378ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
379CFG_DDR_SIZE ?= 0x10000000
380CFG_NS_ENTRY_ADDR ?= 0x80800000
381endif
382
383ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
384CFG_DDR_SIZE ?= 0x10000000
385CFG_UART_BASE ?= UART7_BASE
386endif
387
388ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
389CFG_DDR_SIZE ?= 0xc0000000
390CFG_UART_BASE ?= UART1_BASE
391endif
392
393ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
394CFG_DDR_SIZE ?= 0x80000000
395CFG_UART_BASE ?= UART2_BASE
396endif
397
398ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
399CFG_DDR_SIZE ?= 0x40000000
400CFG_UART_BASE ?= UART3_BASE
401CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
402CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
403endif
404
405ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
406CFG_DDR_SIZE ?= 0x80000000
407CFG_UART_BASE ?= UART2_BASE
408endif
409
410ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
411CFG_DDR_SIZE ?= UL(0x180000000)
412CFG_UART_BASE ?= UART2_BASE
413$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
414$(call force,CFG_CORE_ARM64_PA_BITS,36)
415endif
416
417ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
418CFG_DDR_SIZE ?= UL(0x180000000)
419CFG_UART_BASE ?= UART3_BASE
420CFG_TZDRAM_START ?= 0x56000000
421$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
422$(call force,CFG_CORE_ARM64_PA_BITS,36)
423endif
424
425ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
426CFG_DDR_SIZE ?= 0x80000000
427CFG_UART_BASE ?= UART0_BASE
428CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
429CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
430CFG_CORE_ARM64_PA_BITS ?= 40
431endif
432
433ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxmek))
434CFG_DDR_SIZE ?= 0x40000000
435CFG_UART_BASE ?= UART0_BASE
436$(call force,CFG_MX8DX,y)
437endif
438
439ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
440CFG_DDR_SIZE ?= 0x40000000
441CFG_UART_BASE ?= UART0_BASE
442CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
443CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
444CFG_CORE_ARM64_PA_BITS ?= 40
445endif
446
447ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
448CFG_DDR_SIZE ?= 0x80000000
449CFG_UART_BASE ?= UART5_BASE
450endif
451
452ifneq (,$(filter $(PLATFORM_FLAVOR),mx93evk mx91evk))
453CFG_DDR_SIZE ?= 0x80000000
454CFG_UART_BASE ?= UART1_BASE
455endif
456
457ifneq (,$(filter $(PLATFORM_FLAVOR),mx95evk))
458CFG_DDR_SIZE ?= 0x80000000
459CFG_UART_BASE ?= UART1_BASE
460CFG_NSEC_DDR_1_BASE ?= 0x100000000UL
461CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
462CFG_CORE_ARM64_PA_BITS ?= 40
463endif
464
465# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
466ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
467	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
468include core/arch/arm/cpu/cortex-a9.mk
469
470$(call force,CFG_PL310,y)
471
472CFG_PL310_LOCKED ?= y
473CFG_ENABLE_SCTLR_RR ?= y
474CFG_IMX_SCU ?= y
475endif
476
477ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
478CFG_DRAM_BASE ?= 0x10000000
479endif
480
481ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
482	$(CFG_MX6SX)))
483CFG_DRAM_BASE ?= 0x80000000
484endif
485
486ifeq ($(filter y, $(CFG_MX7)), y)
487CFG_INIT_CNTVOFF ?= y
488CFG_DRAM_BASE ?= 0x80000000
489endif
490
491ifeq ($(filter y, $(CFG_MX7ULP)), y)
492CFG_INIT_CNTVOFF ?= y
493CFG_DRAM_BASE ?= UL(0x60000000)
494$(call force,CFG_IMX_LPUART,y)
495$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
496endif
497
498ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
499$(call force,CFG_GIC,y)
500
501CFG_BOOT_SECONDARY_REQUEST ?= y
502CFG_DT ?= y
503CFG_DTB_MAX_SIZE ?= 0x20000
504CFG_PAGEABLE_ADDR ?= 0
505CFG_PSCI_ARM32 ?= y
506CFG_SECURE_TIME_SOURCE_REE ?= y
507CFG_UART_BASE ?= UART1_BASE
508endif
509
510ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
511$(call force,CFG_IMX_UART,y)
512CFG_IMX_SNVS ?= y
513endif
514
515ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
516CFG_IMX_CSU ?= y
517endif
518
519ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
520CFG_HWSUPP_MEM_PERM_WXN = n
521CFG_IMX_WDOG ?= y
522endif
523
524ifeq ($(CFG_ARM64_core),y)
525# arm-v8 platforms
526include core/arch/arm/cpu/cortex-armv8-0.mk
527$(call force,CFG_ARM_GICV3,y)
528$(call force,CFG_GIC,y)
529$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
530$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
531
532CFG_CRYPTO_WITH_CE ?= y
533
534supported-ta-targets = ta_arm64
535endif
536
537CFG_TZDRAM_SIZE ?= 0x01e00000
538CFG_SHMEM_SIZE ?= 0x00200000
539CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
540CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
541
542# Enable embedded tests by default
543CFG_ENABLE_EMBEDDED_TESTS ?= y
544
545# Set default heap size for imx platforms to 128k
546CFG_CORE_HEAP_SIZE ?= 131072
547
548CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
549CFG_MMAP_REGIONS ?= 24
550
551# SE05X and OCOTP both implement tee_otp_get_die_id()
552ifeq ($(CFG_NXP_SE05X),y)
553$(call force,CFG_IMX_OCOTP,n)
554endif
555CFG_IMX_OCOTP ?= y
556CFG_IMX_DIGPROG ?= y
557CFG_PKCS11_TA ?= y
558
559# Almost all platforms include CAAM HW Modules, except the
560# ones forced to be disabled
561CFG_NXP_CAAM ?= n
562
563ifeq ($(CFG_NXP_CAAM),y)
564ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
565CFG_IMX_SC ?= y
566CFG_IMX_MU ?= y
567endif
568
569else
570
571ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
572CFG_IMX_CAAM ?= y
573endif
574
575endif
576