core: imx: imx6ulevk: handle gic and csu

we use uboot to initialize gic and csu before.
Now switch to let OP-TEE handle them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <i

core: imx: imx6ulevk: handle gic and csu

we use uboot to initialize gic and csu before.
Now switch to let OP-TEE handle them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: imx: Drop CONSOLE_UART_PA_BASE

Drop CONSOLE_UART_PA_BASE

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Sign

core: arm: imx: Drop CONSOLE_UART_PA_BASE

Drop CONSOLE_UART_PA_BASE

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: mx6ulevk: fix CONSOLE_UART_BASE

Fix CONSOLE_UART_BASE, otherwise we will met panic.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewe

core: imx: mx6ulevk: fix CONSOLE_UART_BASE

Fix CONSOLE_UART_BASE, otherwise we will met panic.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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secure storage: update head message when info->dataSize update

When one invokes TEE_WriteObjectData and write some data
into the secure storage file, the data size of the file
may change, but curren

secure storage: update head message when info->dataSize update

When one invokes TEE_WriteObjectData and write some data
into the secure storage file, the data size of the file
may change, but currently it will not update the head
message in persistent objects. This commit will fix this
problem by updating head message when info->dataSize update.

Signed-off-by: Guanchao Liang <liang.guanchao@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: lpae: deal with unaligned regions

Fixes problem in defined memory regions where physical address isn't
pgdir aligned.

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Fixes: 0f8333b888f1 (

core: lpae: deal with unaligned regions

Fixes problem in defined memory regions where physical address isn't
pgdir aligned.

Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Fixes: 0f8333b888f1 ("plat-vexpress/qemu: correct DRAM layout")
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: add core_mmu_divide_block() function

This function divides L1/L2 translation table entry to L2/L3 entries.
It can be used when we need finer mapping than currently possible.

Signed-off-by

core_mmu: add core_mmu_divide_block() function

This function divides L1/L2 translation table entry to L2/L3 entries.
It can be used when we need finer mapping than currently possible.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu_v7: slight refactoring to look like core_mmu_lpae

This patch makes core_mmu_v7.c to look simmilar to core_mmu_lpae.c
- ARMv7-specific definitions was moved from core_mmu_defs.h to .c file

core_mmu_v7: slight refactoring to look like core_mmu_lpae

This patch makes core_mmu_v7.c to look simmilar to core_mmu_lpae.c
- ARMv7-specific definitions was moved from core_mmu_defs.h to .c file
- core_mmu_defs.h was removed, because it stored definitions only for v7
- core_mmu_alloc_l2() now really allocates l2 pages

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: make type_to_attr() function available globally

This function will be used by shared memory subsystem.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklande

core_mmu: make type_to_attr() function available globally

This function will be used by shared memory subsystem.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu.c: introduce add_va_space function

There can be more that one VA space. But old approach does not support
this because there can't be two VA spaces that begin at PA 0x0.

Signed-off-by: Vol

core_mmu.c: introduce add_va_space function

There can be more that one VA space. But old approach does not support
this because there can't be two VA spaces that begin at PA 0x0.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress/qemu: correct DRAM layout.

There are really more memory in qemu config, than configured in
platform_config.h
Invalid DRAM layout causes core_pbuf_is(CORE_MEM_EXTRAM) to fail
when it sh

plat-vexpress/qemu: correct DRAM layout.

There are really more memory in qemu config, than configured in
platform_config.h
Invalid DRAM layout causes core_pbuf_is(CORE_MEM_EXTRAM) to fail
when it should not.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ti: Move load address and increase SHMEM

Move and expand the shared memory allocation as suggested
by the comment above the definition. This should be a safe
place and size for all DRA7 based p

plat-ti: Move load address and increase SHMEM

Move and expand the shared memory allocation as suggested
by the comment above the definition. This should be a safe
place and size for all DRA7 based platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Move console related functions to a separate file

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk

plat-ti: Move console related functions to a separate file

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Add register size definition for serial8250_uart

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@

drivers: Add register size definition for serial8250_uart

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Fixed issues with MMU mapping

The UART is in non-secure IO mem, mark it as such. Also map the
non-secure context in-case we are started with the MMU enabled.

Signed-off-by: Harinarayan Bha

plat-ti: Fixed issues with MMU mapping

The UART is in non-secure IO mem, mark it as such. Also map the
non-secure context in-case we are started with the MMU enabled.

Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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core: arm: support Xilinx ZYNQ7000 ZC702 (plat-zynq7k)

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wi

core: arm: support Xilinx ZYNQ7000 ZC702 (plat-zynq7k)

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: update plat-ls to support secondary core boot

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.

core: arm: update plat-ls to support secondary core boot

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: re-factor plat-imx6

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm: add generic secondary core boot function

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wikla

core: arm: add generic secondary core boot function

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ltc: fix gcc6 warnings

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: encode UUID big endian

When encoding a UUID as a sequence of bytes, the spec
(https://www.ietf.org/rfc/rfc4122.txt) says that the u32, and two u16s
should be represented big endian.

Before th

core: encode UUID big endian

When encoding a UUID as a sequence of bytes, the spec
(https://www.ietf.org/rfc/rfc4122.txt) says that the u32, and two u16s
should be represented big endian.

Before this patch OPTEE always treated them natively. With this patch
UUIDs are always converted to/from big endian when communicating with
normal world.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Fixes: https://github.com/OP-TEE/optee_os/issues/858
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: optee_msg.h include needed .h files

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

mm: drop the forced PL1 RW permissions for user TAs

We have used simple memory access permission model in OP-TEE, if PL1
permission is forced RW, the PL0 permission can only be set to RW or
no acces

mm: drop the forced PL1 RW permissions for user TAs

We have used simple memory access permission model in OP-TEE, if PL1
permission is forced RW, the PL0 permission can only be set to RW or
no access, so the PL0 permission is set to RW in the user TAs which is
not as expected.

Fix it as follow,
1. when TA is in loading process, the PL1 is set to own the RW
permission while the PL0 with no accesss.
2. when the TA is loaded, the PL0 is set to own the required
permissions defined in ta elf program headers and from the access
control model, the PL1 will own the same permissions as the PL0.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

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core: fix pl310 shared mutex registering

Fix missing virtual/physical address conversion. Before this change
the outercache shared mutex was functional only when optee pager was
disable as in such c

core: fix pl310 shared mutex registering

Fix missing virtual/physical address conversion. Before this change
the outercache shared mutex was functional only when optee pager was
disable as in such case shared mutex lied in a flat-mapped memory area
(va==pa). When optee pager is enable (CFG_WITH_PAGER=y), non_linear
mapping of optee core makes optee providing nonsecure world (through
OPTEE_SMC_L2CC_MUTEX_GET_ADDR) an invalid shared mutex physical address.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: assert that mutexes are used from a normal thread only

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etie

core: assert that mutexes are used from a normal thread only

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: assert that no spinlock is held when unmasking IRQs or using a mutex

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
R

core: assert that no spinlock is held when unmasking IRQs or using a mutex

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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