1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <console.h> 31 #include <drivers/imx_uart.h> 32 #include <io.h> 33 #include <kernel/generic_boot.h> 34 #include <kernel/panic.h> 35 #include <kernel/pm_stubs.h> 36 #include <mm/core_mmu.h> 37 #include <mm/core_memprot.h> 38 #include <platform_config.h> 39 #include <stdint.h> 40 #include <sm/optee_smc.h> 41 #include <tee/entry_fast.h> 42 #include <tee/entry_std.h> 43 44 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 45 defined(PLATFORM_FLAVOR_mx6qsabresd) 46 #include <drivers/gic.h> 47 #include <kernel/tz_ssvce_pl310.h> 48 #endif 49 50 static void main_fiq(void); 51 52 static const struct thread_handlers handlers = { 53 .std_smc = tee_entry_std, 54 .fast_smc = tee_entry_fast, 55 .fiq = main_fiq, 56 .cpu_on = pm_panic, 57 .cpu_off = pm_panic, 58 .cpu_suspend = pm_panic, 59 .cpu_resume = pm_panic, 60 .system_off = pm_panic, 61 .system_reset = pm_panic, 62 }; 63 64 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 65 defined(PLATFORM_FLAVOR_mx6qsabresd) 66 static struct gic_data gic_data; 67 68 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 69 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 70 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 71 #endif 72 73 const struct thread_handlers *generic_boot_get_handlers(void) 74 { 75 return &handlers; 76 } 77 78 static void main_fiq(void) 79 { 80 panic(); 81 } 82 83 static vaddr_t console_base(void) 84 { 85 static void *va; 86 87 if (cpu_mmu_enabled()) { 88 if (!va) 89 va = phys_to_virt(CONSOLE_UART_PA_BASE, 90 MEM_AREA_IO_NSEC); 91 return (vaddr_t)va; 92 } 93 return CONSOLE_UART_BASE; 94 } 95 96 void console_init(void) 97 { 98 vaddr_t base = console_base(); 99 100 imx_uart_init(base); 101 } 102 103 void console_putc(int ch) 104 { 105 vaddr_t base = console_base(); 106 107 /* If \n, also do \r */ 108 if (ch == '\n') 109 imx_uart_putc('\r', base); 110 imx_uart_putc(ch, base); 111 } 112 113 void console_flush(void) 114 { 115 vaddr_t base = console_base(); 116 117 imx_uart_flush_tx_fifo(base); 118 } 119 120 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \ 121 defined(PLATFORM_FLAVOR_mx6qsabresd) 122 vaddr_t pl310_base(void) 123 { 124 static void *va __data; /* in case it's used before .bss is cleared */ 125 126 if (cpu_mmu_enabled()) { 127 if (!va) 128 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 129 return (vaddr_t)va; 130 } 131 return PL310_BASE; 132 } 133 134 void main_init_gic(void) 135 { 136 vaddr_t gicc_base; 137 vaddr_t gicd_base; 138 139 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 140 MEM_AREA_IO_SEC); 141 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 142 MEM_AREA_IO_SEC); 143 144 if (!gicc_base || !gicd_base) 145 panic(); 146 147 /* Initialize GIC */ 148 gic_init(&gic_data, gicc_base, gicd_base); 149 150 itr_init(&gic_data.chip); 151 } 152 #endif 153