core: move mmap trace into a specific routine

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: fix memory mapping overlapping sequence

Before this patch, the overlapping memory ranges where detected
only if the lower physical range was registered before the
higher overlapping physical r

core: fix memory mapping overlapping sequence

Before this patch, the overlapping memory ranges where detected
only if the lower physical range was registered before the
higher overlapping physical range.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: fix plat-stm iomem mapping

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: remove useless rounding for registered io memory

This change removes useless rounding on registered io memory for
the platforms maintained by Linaro.

Also remove registering of GIC iomem on p

core: remove useless rounding for registered io memory

This change removes useless rounding on registered io memory for
the platforms maintained by Linaro.

Also remove registering of GIC iomem on plat-mediatek as the platform
does not use the GIC resources.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: deprecate DEVICEx_TYPE/_PA_BASE/_SIZE

Macros DEVICEx_TYPE, DEVICEx_PA_BASE and DEVICEx__SIZE used to
help platform to register their address range mapping requirements.
These are now deprecate

core: deprecate DEVICEx_TYPE/_PA_BASE/_SIZE

Macros DEVICEx_TYPE, DEVICEx_PA_BASE and DEVICEx__SIZE used to
help platform to register their address range mapping requirements.
These are now deprecated since platform should use the more flexible
register_phys_mem() macro.

This change removes all occurrences of DEVICEx_TYPE/_PA_BASE/_SIZE
and use the register_phys_mem() instead.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: fix register_XXX_mem() against physical address

Use __COUNTER__ instead of the registered physical address to
generate the label of the structure defined by the macros
__register_phys_mem() an

core: fix register_XXX_mem() against physical address

Use __COUNTER__ instead of the registered physical address to
generate the label of the structure defined by the macros
__register_phys_mem() and __register_sdp_mem().

Before this change, when argument "addr" is used, one cannot use these
macros providing an address that is the result of a local operation.

I.e This implementation was not possible:
__register_phys_mem(<any-id>, ROUNDUP(<addr>, <value>), <size>);
and one needed to use a temporary macro for the address computation:
#define MY_BASE_ADDRESS ROUNDUP(<addr>, <value>)
__register_phys_mem(<any-id>, MY_BASE_ADDRESS, <size>);

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: FS: remove redundant fields from struct tee_svc_storage_head

Removes the unused/redundant fields magic, head_size, ds_size from
struct tee_svc_storage_head. meta_size is renamed to attr_size t

core: FS: remove redundant fields from struct tee_svc_storage_head

Removes the unused/redundant fields magic, head_size, ds_size from
struct tee_svc_storage_head. meta_size is renamed to attr_size to better
reflect the usage.

The size of the data stream is calculated from the total size of the
file minus attr_size. This makes the header static after it's
initialized.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: FS: let FOP->create() initialize the new file

Moves the code from syscall_storage_obj_create() that does several calls
via the FOP interface into FOP->create() instead. With this all updates
c

core: FS: let FOP->create() initialize the new file

Moves the code from syscall_storage_obj_create() that does several calls
via the FOP interface into FOP->create() instead. With this all updates
can be performed while the mutex is held. This makes the create
operation easier to optimize as each call via the FOP interface is
atomic.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

tee_mm: add locking while working with pool->entry

This fixes race condition in linked list handling.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wik

tee_mm: add locking while working with pool->entry

This fixes race condition in linked list handling.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

spinlock: add cpu_spin_lock_xsave()/xrestore() functions

These are functions like spin_lock_irqsave() functions in linux kernel.
They should replace xxx_lock() functions in different modules.

Signe

spinlock: add cpu_spin_lock_xsave()/xrestore() functions

These are functions like spin_lock_irqsave() functions in linux kernel.
They should replace xxx_lock() functions in different modules.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: increase size of the exception stack in AArch32 mode

'stack_abt' is too small when pager is enabled and needs to be increased.
'stack_abt' is used for aborts (prefetch/data/undef) and native/f

core: increase size of the exception stack in AArch32 mode

'stack_abt' is too small when pager is enabled and needs to be increased.
'stack_abt' is used for aborts (prefetch/data/undef) and native/foreign
interruptions exceptions.

Tests on ARMv7 targets show that between 1000 and 1500 bytes of these
stacks are consumed at runtime. Tests considered configurations with
trace/debug/LPAE/VFP enabled and disabled. Tests were based on running
OP-TEE with the xtest non-regression suite.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Tested-by: Etienne Carriere <etienne.carriere@st.com> (qemu_virt/b2260)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core_mmu: round VAs to region size

Entries in memory map are sorted by address, not by region size.
So, if entries have region size 2M, 4k, 2M, ... then all
maps after second one will be misaligned.

core_mmu: round VAs to region size

Entries in memory map are sorted by address, not by region size.
So, if entries have region size 2M, 4k, 2M, ... then all
maps after second one will be misaligned. Thus, we need to
explicitly round virtual addresses.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt)

show more ...

drivers: scif: enable TX during initialization

Newer version of TF disables TX and RX modules of SCIF before
jumping to OP-TEE. We need to enable TX back.

Signed-off-by: Volodymyr Babchuk <vlad.bab

drivers: scif: enable TX during initialization

Newer version of TF disables TX and RX modules of SCIF before
jumping to OP-TEE. We need to enable TX back.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: fix compile error with CFG_WITH_USER_TA=n

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Fixes: 040bc0f04138 ("core: add test case for hash-tree")
Signed-off-by: Jens Wiklander <j

core: fix compile error with CFG_WITH_USER_TA=n

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Fixes: 040bc0f04138 ("core: add test case for hash-tree")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: add test case for hash-tree

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@

core: add test case for hash-tree

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: FS: htree: fix undo update

Updates of the hash-tree can be undone by closing the hash-tree before
tee_fs_htree_sync_to_storage() is called.

Before this patch the hash-tree was left in a half

core: FS: htree: fix undo update

Updates of the hash-tree can be undone by closing the hash-tree before
tee_fs_htree_sync_to_storage() is called.

Before this patch the hash-tree was left in a half updated state if
tee_fs_htree_close() was called before tee_fs_htree_sync_to_storage().

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: FS: htree: add rpc final callbacks

Adds rpc final callbacks to struct tee_fs_htree_storage to make the it
possible to isolate the hash tree implementation for test.

Reviewed-by: Etienne Carri

core: FS: htree: add rpc final callbacks

Adds rpc final callbacks to struct tee_fs_htree_storage to make the it
possible to isolate the hash tree implementation for test.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: fix typo in pager mapping setup

This change fixes a typo in the core mapping setup when pager is enabled.
Looking back in OP-TEE history shows this typo has been there since quite
a while howe

core: fix typo in pager mapping setup

This change fixes a typo in the core mapping setup when pager is enabled.
Looking back in OP-TEE history shows this typo has been there since quite
a while however various build tests based on old code showed the previous
buggy implementation luckily gave valid settings. Yet, it looks far
better once fixed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: move plat-stm consoles to generic console framework

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: move stih UART driver to the drivers/ directory

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: arm: imx use early bss attribute for static variable

Use __early_bss attribute for the static variable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jerome Forissier <jerome.foriss

core: arm: imx use early bss attribute for static variable

Use __early_bss attribute for the static variable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: fix console drivers against pager

Console operations structures must be kept in the unpaged sections
when pager is enable.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Review

core: fix console drivers against pager

Console operations structures must be kept in the unpaged sections
when pager is enable.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt)

show more ...

plat-vexpress: move QEMU SDP test memory to end of the secure RAM

This change restores qemu_armv8 OP-TEE base address to 1Mbyte after
secure RAM base address and moves the qemu_virt and qemu_armv8 S

plat-vexpress: move QEMU SDP test memory to end of the secure RAM

This change restores qemu_armv8 OP-TEE base address to 1Mbyte after
secure RAM base address and moves the qemu_virt and qemu_armv8 SDP
test memory pool to the end of the secure RAM. SDP memory pool
size is increased to 4MByte. TA RAM size is decreased according
to these changes.

Qemu_armv8 reserves the first 1Mbyte of secure RAM to the ARM-TF.
This change fixes the regression introduced by commit df05d4ea7d58
("plat-vexpress: define SDP memory") that assigned back this 1Mbyte
to OP-TEE or SDP memory.

Fixes: df05d4ea7d58 ("plat-vexpress: define SDP memory")
Reported-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt/_armv8)

show more ...

core: arm: imx: correct PCR settings

According to Cortex A9 TRM, bit[10:8] of PCR is max_clk_latency:
Samples the value present on the MAXCLKLATENCY pins on exit from reset.
This value reflects an i

core: arm: imx: correct PCR settings

According to Cortex A9 TRM, bit[10:8] of PCR is max_clk_latency:
Samples the value present on the MAXCLKLATENCY pins on exit from reset.
This value reflects an implementation-specific parameter.
ARM strongly recommends that the software does not modify it.

So change the value to 0 is not wise, correct it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: arm: add support for i.MX6 Dual Lite SabreSD

Signed-off-by: Mathieu Briand <mbriand@witekio.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.car

core: arm: add support for i.MX6 Dual Lite SabreSD

Signed-off-by: Mathieu Briand <mbriand@witekio.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

show more ...