1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <assert.h> 29 #include <drivers/imx_uart.h> 30 #include <io.h> 31 #include <keep.h> 32 #include <util.h> 33 34 /* Register definitions */ 35 #define URXD 0x0 /* Receiver Register */ 36 #define UTXD 0x40 /* Transmitter Register */ 37 #define UCR1 0x80 /* Control Register 1 */ 38 #define UCR2 0x84 /* Control Register 2 */ 39 #define UCR3 0x88 /* Control Register 3 */ 40 #define UCR4 0x8c /* Control Register 4 */ 41 #define UFCR 0x90 /* FIFO Control Register */ 42 #define USR1 0x94 /* Status Register 1 */ 43 #define USR2 0x98 /* Status Register 2 */ 44 #define UESC 0x9c /* Escape Character Register */ 45 #define UTIM 0xa0 /* Escape Timer Register */ 46 #define UBIR 0xa4 /* BRM Incremental Register */ 47 #define UBMR 0xa8 /* BRM Modulator Register */ 48 #define UBRC 0xac /* Baud Rate Count Register */ 49 #define UTS 0xb4 /* UART Test Register (mx31) */ 50 51 /* UART Control Register Bit Fields.*/ 52 #define URXD_CHARRDY (1<<15) 53 #define URXD_ERR (1<<14) 54 #define URXD_OVRRUN (1<<13) 55 #define URXD_FRMERR (1<<12) 56 #define URXD_BRK (1<<11) 57 #define URXD_PRERR (1<<10) 58 #define URXD_RX_DATA (0xFF) 59 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 60 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 61 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 62 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 63 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 64 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 65 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 66 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 67 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 68 #define UCR1_SNDBRK (1<<4) /* Send break */ 69 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 70 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 71 #define UCR1_DOZE (1<<1) /* Doze */ 72 #define UCR1_UARTEN (1<<0) /* UART enabled */ 73 74 #define UTS_FRCPERR (1<<13) /* Force parity error */ 75 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 76 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 77 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 78 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 79 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 80 #define UTS_SOFTRST (1<<0) /* Software reset */ 81 82 static vaddr_t chip_to_base(struct serial_chip *chip) 83 { 84 struct imx_uart_data *pd = 85 container_of(chip, struct imx_uart_data, chip); 86 87 return io_pa_or_va(&pd->base); 88 } 89 90 static void imx_uart_flush(struct serial_chip *chip) 91 { 92 vaddr_t base = chip_to_base(chip); 93 94 while (!(read32(base + UTS) & UTS_TXEMPTY)) 95 ; 96 } 97 98 static int imx_uart_getchar(struct serial_chip *chip) 99 { 100 vaddr_t base = chip_to_base(chip); 101 102 while (read32(base + UTS) & UTS_RXEMPTY) 103 ; 104 105 return (read32(base + URXD) & URXD_RX_DATA); 106 } 107 108 static void imx_uart_putc(struct serial_chip *chip, int ch) 109 { 110 vaddr_t base = chip_to_base(chip); 111 112 write32(ch, base + UTXD); 113 114 /* Wait until sent */ 115 while (!(read32(base + UTS) & UTS_TXEMPTY)) 116 ; 117 } 118 119 static const struct serial_ops imx_uart_ops = { 120 .flush = imx_uart_flush, 121 .getchar = imx_uart_getchar, 122 .putc = imx_uart_putc, 123 }; 124 KEEP_PAGER(imx_uart_ops); 125 126 void imx_uart_init(struct imx_uart_data *pd, paddr_t base) 127 { 128 pd->base.pa = base; 129 pd->chip.ops = &imx_uart_ops; 130 131 /* 132 * Do nothing, debug uart(uart0) share with normal world, 133 * everything for uart0 initialization is done in bootloader. 134 */ 135 } 136