core: fix print_kernel_stack()

Previously was print_kernel_stack() supplying zeroes instead of real
values for start and size of exidx tables needed for unwind. With this
patch are correct values f

core: fix print_kernel_stack()

Previously was print_kernel_stack() supplying zeroes instead of real
values for start and size of exidx tables needed for unwind. With this
patch are correct values for exidx and exidx_sz supplied.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Fixes: 31a2964 ("core: dump call stack of user TAs on abort")
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: fix tee_pager_set_uta_area_attr()

Adds missing synchronization, dsb_ishst(), required to make sure that
translation table update is visible after the final update of the
attributes of a

core: pager: fix tee_pager_set_uta_area_attr()

Adds missing synchronization, dsb_ishst(), required to make sure that
translation table update is visible after the final update of the
attributes of a page.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Generate binaries for loaders supporting separate binary loading

Generate three binaries tee-header_v2.bin, tee-pager_v2.bin and
tee-pageable_v2.bin for loaders supporting separate binary loading.
T

Generate binaries for loaders supporting separate binary loading

Generate three binaries tee-header_v2.bin, tee-pager_v2.bin and
tee-pageable_v2.bin for loaders supporting separate binary loading.
This kind of loader loads and parses header binary first and then
loads rest two binaries under specified manners header information
implies. Generic loaders who don't support separate binary loading
just ignore these binaries; and this change will not affect all
existing design.

Signed-off-by: Summer Qin <summer.qin@arm.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: demote a couple of messages from IMSG() to DMSG()

The first and and fourth lines in the boot sequence below are debug
messages that should not be printed when the log level is INFO:

INFO:

core: demote a couple of messages from IMSG() to DMSG()

The first and and fourth lines in the boot sequence below are debug
messages that should not be printed when the log level is INFO:

INFO: TEE-CORE: No NSEC DDR memory area defined
INFO: TEE-CORE:
INFO: TEE-CORE: OP-TEE version: 2.5.0-rc1 #1 Wed Jun 28 15:11:06 UTC 2017 aarch64
INFO: TEE-CORE: Shared memory address range: 3dc00000, 3f000000
INFO: TEE-CORE: Initialized

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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arm: imx: add i.MX7D support

Add i.MX7D support.
- Add register definition
- Add gpcv2 to powerup and powerdown cpu
- Introduce soc runtime detection, the final goal is to support i.MX
family

arm: imx: add i.MX7D support

Add i.MX7D support.
- Add register definition
- Add gpcv2 to powerup and powerdown cpu
- Introduce soc runtime detection, the final goal is to support i.MX
family using one image, but still far from it. Now using the runtime
detection, we could remove the CFG_MX[6,7][x] to simplify the code,
such as in imx psci cpu on/off using one function to support 6Q/7D
without CFG_[X].
- Add PSCI cpu/off/affinity

The scripts to build 7dsdb image.
make PLATFORM=imx-mx7dsabresd \
mkimage -A arm -O linux -C none -a 0xbdffffe4 -e 0xbe000000 \
-d out/arm-plat-imx/core/tee.bin uTee-7d

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add compile check for CFG_TEE_RAM_VA_SIZE

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: add comment, modify error message]

core: add compile check for CFG_TEE_RAM_VA_SIZE

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
[jf: add comment, modify error message]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: relax verify_special_mem_areas()

Relaxes verify_special_mem_areas() with regards to MEM_AREA_RAM_NSEC and
MEM_AREA_NSEC_SHM. Those two regions are from now on allowed to overlap
as any overlap

core: relax verify_special_mem_areas()

Relaxes verify_special_mem_areas() with regards to MEM_AREA_RAM_NSEC and
MEM_AREA_NSEC_SHM. Those two regions are from now on allowed to overlap
as any overlap there is harmless and more trouble than it's worth to
avoid.

Fixes problem with panic() when booting on FVP.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Fixes: 70cdca357de9 ("plat-vexpress: use register_nsec_ddr()")
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: REE FS: use RPMB for hash storage

REE FS uses RPMB (if available) for storage of dirfile hash.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Volodymyr Babchuk <vlad.babch

core: REE FS: use RPMB for hash storage

REE FS uses RPMB (if available) for storage of dirfile hash.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: RPMB FS: provide tee_rpmb_fs_raw_open()

Provides tee_rpmb_fs_raw_open() use by OP-TEE OS.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Volodymyr Babchuk <vlad.babchuk@gm

core: RPMB FS: provide tee_rpmb_fs_raw_open()

Provides tee_rpmb_fs_raw_open() use by OP-TEE OS.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: REE FS: close dirfile on error

REE FS closes the dirfile if returning error from a function that may
have changed the content of a secure storage object. This effectively
undoes previous opera

core: REE FS: close dirfile on error

REE FS closes the dirfile if returning error from a function that may
have changed the content of a secure storage object. This effectively
undoes previous operation.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: FS: add hash parameter to dirfile interface

Adds a hash parameter to the dirfile interface. The hash is used in the
same way as in the htree interface, that is, used to verify integrity on
ope

core: FS: add hash parameter to dirfile interface

Adds a hash parameter to the dirfile interface. The hash is used in the
same way as in the htree interface, that is, used to verify integrity on
open and used to get updated hash on writes.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: rename TLB maintenance files

ssvce_aXX.S and tz_ssvce.h now only provide TLB maintenance support.
This change renames the source and header files accordingly.

Signed-off-by: Etienne Carr

core: arm: rename TLB maintenance files

ssvce_aXX.S and tz_ssvce.h now only provide TLB maintenance support.
This change renames the source and header files accordingly.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: ssvce_a32.S, ssvce_a64.S: remove useless includes/comments

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-b

core: arm: ssvce_a32.S, ssvce_a64.S: remove useless includes/comments

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: tz_ssvce.h: remove deprecated declarations

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklande

core: arm: tz_ssvce.h: remove deprecated declarations

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx: add 6ULL EVK support

Add i.MX6 ULL EVK support.
i.MX6ULL is derivative from i.MX6UL, so reuse some code for i.MX6UL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Car

core: arm: imx: add 6ULL EVK support

Add i.MX6 ULL EVK support.
i.MX6ULL is derivative from i.MX6UL, so reuse some code for i.MX6UL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx6ul: add platform early init code

Add platform early init code.

Configure ACTLR to enable SMP.
Configure NSACR to let NS could access cp10/cp11 and NS_SMP.

Signed-off-by: Peng Fan <p

core: arm: imx6ul: add platform early init code

Add platform early init code.

Configure ACTLR to enable SMP.
Configure NSACR to let NS could access cp10/cp11 and NS_SMP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx6ul: switch to use CFG_SECURE_TIME_SOURCE_REE

Switch to use CFG_SECURE_TIME_SOURCE_REE.
Since we do not have RTC, and arm counter will lose power when suspend,
we use CFG_SECURE_TIME_SOURCE

core: imx6ul: switch to use CFG_SECURE_TIME_SOURCE_REE

Switch to use CFG_SECURE_TIME_SOURCE_REE.
Since we do not have RTC, and arm counter will lose power when suspend,
we use CFG_SECURE_TIME_SOURCE_REE now.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx support psci off and affinity

Support psci off and affinity.
To i.MX6, CPU could not offline itself, so needs to use core0 to
offline other cores.

Introduce imx-common.c to include t

core: arm: imx support psci off and affinity

Support psci off and affinity.
To i.MX6, CPU could not offline itself, so needs to use core0 to
offline other cores.

Introduce imx-common.c to include the common code for i.MX family,
SRC operation is used by i.MX6/7, so move them to imx-common.c

Use CFG_BOOT_SECONDARY_REQUEST to wrap the psci_cpu_on/off/affinity
functions, these functions are only needed by SMP systems.To i.MX6UL,
they are not needed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx: use one imx-regs.h file

Clean up to use one imx-regs.h for i.MX SoC family.
If there are different IP address, use CFG_MX6[Q,D,UL]
and etc to differentiate them.

Signed-off-by: Peng

core: arm: imx: use one imx-regs.h file

Clean up to use one imx-regs.h for i.MX SoC family.
If there are different IP address, use CFG_MX6[Q,D,UL]
and etc to differentiate them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: mx6ulevk: refine the tee address map

There is 512M DDR Memory on i.MX6UL-EVK board.
Reserve high 32M for TEE usage. The highest 2M for SHMEM.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
A

core: arm: mx6ulevk: refine the tee address map

There is 512M DDR Memory on i.MX6UL-EVK board.
Reserve high 32M for TEE usage. The highest 2M for SHMEM.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: psci: add helper functions

Add helper function psci_armv7_cpu_off.
This function will be used when use psci to offline a cpu.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etie

core: arm: psci: add helper functions

Add helper function psci_armv7_cpu_off.
This function will be used when use psci to offline a cpu.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix TODOs related to TLB maintenance in the pager

Invalidate TLBs for target references instead of invalidating the
whole tables.

Some changes affect places where several references are modif

core: fix TODOs related to TLB maintenance in the pager

Invalidate TLBs for target references instead of invalidating the
whole tables.

Some changes affect places where several references are modified and
must be invalidated in the TLBs. This change aims at lowering the
synchronization barrier required before/after the TLB maintenance
operations.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch{32,64} pager)

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core: deprecate core_tlb_maintenance()

The core_tlb_maintenance() indirection is not useful. This function is
now deprecated and one shall straight call tlbi_xxx() function instead.

Signed-off-by:

core: deprecate core_tlb_maintenance()

The core_tlb_maintenance() indirection is not useful. This function is
now deprecated and one shall straight call tlbi_xxx() function instead.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix AArch64 implementation of tlbi_asid()

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add TLB invalidation by-mva-all-asid

tlbi_mva_allasid(): TLB invalidation by MVA for all ASID with all
synchronisation support.

tlbi_mva_allasid_nosync(): same invalidation but without the
sy

core: add TLB invalidation by-mva-all-asid

tlbi_mva_allasid(): TLB invalidation by MVA for all ASID with all
synchronisation support.

tlbi_mva_allasid_nosync(): same invalidation but without the
synchronization barriers.

Remove tlbi_mva_curasid that was disabled and not used.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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