1 /* 2 * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <common.h> 29 #include <console.h> 30 #include <cru.h> 31 #include <grf.h> 32 #include <initcall.h> 33 #include <io.h> 34 #include <kernel/delay.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <mm/core_mmu.h> 38 #include <mm/core_memprot.h> 39 #include <platform_config.h> 40 #include <sm/optee_smc.h> 41 #include <sm/psci.h> 42 #include <stdint.h> 43 #include <tee/entry_std.h> 44 #include <tee/entry_fast.h> 45 46 static bool wait_core_wfe_i(uint32_t core) 47 { 48 uint32_t wfei_mask, loop = 0; 49 vaddr_t va_base = (vaddr_t)phys_to_virt_io(GRF_BASE); 50 51 wfei_mask = CORE_WFE_I_MASK(core); 52 while (!(read32(va_base + GRF_CPU_STATUS1) & wfei_mask) && loop < 500) { 53 udelay(2); 54 loop++; 55 } 56 57 return read32(va_base + GRF_CPU_STATUS1) & wfei_mask; 58 } 59 60 static bool core_held_in_reset(uint32_t core) 61 { 62 uint32_t val; 63 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 64 65 val = read32(va_base + CRU_SOFTRST_CON(0)); 66 67 return val & CORE_HELD_IN_RESET(core); 68 } 69 70 uint32_t psci_version(void) 71 { 72 return PSCI_VERSION_1_0; 73 } 74 75 int psci_cpu_on(uint32_t core_idx, uint32_t entry, 76 uint32_t context_id __unused) 77 { 78 bool wfei; 79 vaddr_t cru_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 80 vaddr_t isram_base = (vaddr_t)phys_to_virt_io(ISRAM_BASE); 81 82 core_idx &= MPIDR_CPU_MASK; 83 if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE)) 84 return PSCI_RET_INVALID_PARAMETERS; 85 86 DMSG("core_id: %" PRIu32, core_idx); 87 88 /* set secondary cores' NS entry addresses */ 89 ns_entry_addrs[core_idx] = entry; 90 91 /* wait */ 92 if (!core_held_in_reset(core_idx)) { 93 wfei = wait_core_wfe_i(core_idx); 94 if (!wfei) { 95 EMSG("Can't wait cpu%" PRIu32 " wfei before softrst", 96 core_idx); 97 return PSCI_RET_DENIED; 98 } 99 } 100 101 /* soft reset core */ 102 write32(CORE_SOFT_RESET(core_idx), cru_base + CRU_SOFTRST_CON(0)); 103 dsb(); 104 105 udelay(2); 106 107 /* soft release core */ 108 write32(CORE_SOFT_RELEASE(core_idx), cru_base + CRU_SOFTRST_CON(0)); 109 dsb(); 110 111 /* wait */ 112 wfei = wait_core_wfe_i(core_idx); 113 if (!wfei) { 114 EMSG("Can't wait cpu%" PRIu32 " wfei after softrst", core_idx); 115 return PSCI_RET_DENIED; 116 } 117 118 /* set secondary secure entry address and lock tag */ 119 write32(CFG_TEE_LOAD_ADDR, isram_base + BOOT_ADDR_OFFSET); 120 write32(LOCK_TAG, isram_base + LOCK_ADDR_OFFSET); 121 dsb(); 122 123 sev(); 124 dsb(); 125 126 return PSCI_RET_SUCCESS; 127 } 128 129 int psci_cpu_off(void) 130 { 131 uint32_t core = get_core_pos(); 132 133 if ((core == 0) || (core >= CFG_TEE_CORE_NB_CORE)) 134 return PSCI_RET_INVALID_PARAMETERS; 135 136 DMSG("core_id: %" PRIu32, core); 137 138 psci_armv7_cpu_off(); 139 thread_mask_exceptions(THREAD_EXCP_ALL); 140 141 while (1) 142 wfi(); 143 144 return PSCI_RET_INTERNAL_FAILURE; 145 } 146 147 int psci_affinity_info(uint32_t affinity, 148 uint32_t lowest_affnity_level __unused) 149 { 150 uint32_t core_idx = affinity & MPIDR_CPU_MASK; 151 uint32_t wfi_mask = CORE_WFI_MASK(core_idx); 152 vaddr_t va_base = (vaddr_t)phys_to_virt_io(GRF_BASE); 153 154 DMSG("core_id: %" PRIu32 " STATUS: %" PRIx32 " MASK: %" PRIx32, 155 core_idx, read32(va_base + GRF_CPU_STATUS1), wfi_mask); 156 157 return (read32(va_base + GRF_CPU_STATUS1) & wfi_mask) ? 158 PSCI_AFFINITY_LEVEL_OFF : PSCI_AFFINITY_LEVEL_ON; 159 } 160 161 void psci_system_reset(void) 162 { 163 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 164 165 /* PLLs enter slow mode */ 166 write32(PLLS_SLOW_MODE, va_base + CRU_MODE_CON); 167 dsb(); 168 169 /* Global second reset */ 170 write32(CRU_SNDRST_VAL, va_base + CRU_SNDRST_VAL_BASE); 171 dsb(); 172 } 173 174 /* When SMP bootup, we release cores one by one */ 175 static TEE_Result reset_nonboot_cores(void) 176 { 177 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 178 179 write32(NONBOOT_CORES_SOFT_RESET, va_base + CRU_SOFTRST_CON(0)); 180 181 return TEE_SUCCESS; 182 } 183 184 service_init_late(reset_nonboot_cores); 185