History log of /optee_os/core/ (Results 4676 – 4700 of 6456)
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6dbb931a05-May-2018 Christopher Co <christopher.co@microsoft.com>

plat-imx: Add i.MX6SoloX Udoo Neo Full platform flavor

Add support for i.MX6SoloX Udoo Neo Full.
https://shop.udoo.org/usa/neo/udoo-neo-full.html

Signed-off-by: Christopher Co <christopher.co@micro

plat-imx: Add i.MX6SoloX Udoo Neo Full platform flavor

Add support for i.MX6SoloX Udoo Neo Full.
https://shop.udoo.org/usa/neo/udoo-neo-full.html

Signed-off-by: Christopher Co <christopher.co@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>

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4e10cbd525-Sep-2018 Jordan Rhee <jordanrh@microsoft.com>

plat-imx: add mx7dclsom platform flavor

Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

40784ed026-Sep-2018 Jordan Rhee <jordanrh@microsoft.com>

plat-imx: fix compile error for mx6qhmbedge flavor

Set DDR sze and console UART base in conf.mk to
avoid a compilation error.

Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan R

plat-imx: fix compile error for mx6qhmbedge flavor

Set DDR sze and console UART base in conf.mk to
avoid a compilation error.

Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Acked-by: Peng Fan <peng.fan@nxp.com>

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078b214a18-Oct-2018 Jerome Forissier <jerome.forissier@linaro.org>

qemu: increase CFG_DTB_MAX_SIZE to 1 MiB

Since upstream QEMU commit 14ec3cbd7c1e ("device_tree: Increase
FDT_MAX_SIZE to 1 MiB"), which is included in release v2.12.1 and later,
OP-TEE initializatio

qemu: increase CFG_DTB_MAX_SIZE to 1 MiB

Since upstream QEMU commit 14ec3cbd7c1e ("device_tree: Increase
FDT_MAX_SIZE to 1 MiB"), which is included in release v2.12.1 and later,
OP-TEE initialization fails with the following error (-3 is
-FDT_ERR_NOSPACE):

E/TC:0 0 init_fdt:808 Invalid Device Tree at 0x40000000: error -3

Increase CFG_DTB_MAX_SIZE accordingly. Tested with the current tip of the
QEMU master branch, in 32- and 64-bit modes (note that our 64-bit QEMU
setup needs a TF-A patch -- PLAT_QEMU_DT_MAX_SIZE needs to be set to 1 MiB
too).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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cd278f7819-Oct-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: simplify shm cookie handling

Simplifies SHM cookie handling by storing the cookie in the mobj instead
of putting the burden on the caller. The cookie parameter is dropped
from the thread_rpc_*

core: simplify shm cookie handling

Simplifies SHM cookie handling by storing the cookie in the mobj instead
of putting the burden on the caller. The cookie parameter is dropped
from the thread_rpc_*_payload() functions. All callers of those
functions are also updated and unused cookie members of related structs
are removed too.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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82e1d96324-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: thread: thread_rpc_{free,alloc}_arg() static

Makes thread_rpc_alloc_arg() and thread_rpc_free_arg() static since they
are only used internally in thread.c

Reviewed-by: Jerome Forissier <jerom

core: thread: thread_rpc_{free,alloc}_arg() static

Makes thread_rpc_alloc_arg() and thread_rpc_free_arg() static since they
are only used internally in thread.c

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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cc459a4219-Oct-2018 Victor Chong <victor.chong@linaro.org>

hikey960: change DRAM1_SIZE_NSEC for 4GB board

SoC reference manual [1] page 2-23 says that the DRAM address range is
0x00000000 - 0xDFFFFFFF for a total of 3.5GB, so the limit would seem
to be 0xE0

hikey960: change DRAM1_SIZE_NSEC for 4GB board

SoC reference manual [1] page 2-23 says that the DRAM address range is
0x00000000 - 0xDFFFFFFF for a total of 3.5GB, so the limit would seem
to be 0xE0000000, not 0x100000000, or 0xFFE00000 based on [2] and [3].

Link: [1] https://github.com/96boards/documentation/raw/master/consumer/hikey/hikey960/hardware-docs/HiKey960_SoC_Reference_Manual.pdf
Link: [2] https://github.com/OP-TEE/optee_os/issues/2597#issuecomment-428587050
Link: [3] https://github.com/OP-TEE/optee_os/issues/2597#issuecomment-428865951
Fixes: https://github.com/OP-TEE/optee_os/issues/2597
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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daaf4f1112-Oct-2018 Daniel McIlvaney <damcilva@microsoft.com>

core: modify tee_otp_get_hw_unique_key to return TEE_Result

Getting the hardware key can fail on some platforms. Modify the function
signature to return an appropriate error code.

Signed-off-by: Da

core: modify tee_otp_get_hw_unique_key to return TEE_Result

Getting the hardware key can fail on some platforms. Modify the function
signature to return an appropriate error code.

Signed-off-by: Daniel McIlvaney <damcilva@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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9551f4e508-Oct-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: juno: workaround cortex-a57 errata 808870

Workaround errata 808870:
Unconditional VLDM instructions might cause an alignment fault even
though the address is aligned

Products Affected: Cortex

core: juno: workaround cortex-a57 errata 808870

Workaround errata 808870:
Unconditional VLDM instructions might cause an alignment fault even
though the address is aligned

Products Affected: Cortex-A57 MPCore.
Present in: r0p0

The workaround is to avoid generating the problematic instructions in
AArch32 TA.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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405c67d305-Oct-2018 Jens Wiklander <jens.wiklander@linaro.org>

abort.c: arm32: assume VFP instr if undef

If an undefined instruction exception is raised from user mode assume it
is a VFP instruction unless VFP already is enabled.

This avoids reading user mode

abort.c: arm32: assume VFP instr if undef

If an undefined instruction exception is raised from user mode assume it
is a VFP instruction unless VFP already is enabled.

This avoids reading user mode memory while handling an abort which until
now has kept an undiscovered race where a page could become inaccessible
before the abort handler had the chance to read the instruction from the
page.

There is room for false positives. Those will be discovered the next
time the instruction is executed and still causes an undefined
instruction exception. Only this time VFP is already enabled so we know
it's not a VFP instruction. Enabling VFP in vain like this is harmless.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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b2322fd304-Oct-2018 Etienne Carriere <etienne.carriere@st.com>

core: prevent allocation when exception index tables are empty

This change prevent the core from allocating memory, mapping and
other resources to map exception index tables that are all empty.

Sig

core: prevent allocation when exception index tables are empty

This change prevent the core from allocating memory, mapping and
other resources to map exception index tables that are all empty.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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1330634625-Sep-2018 Etienne Carriere <etienne.carriere@st.com>

core: correct time conversion in delay support

The previous code may overflow in 32bit architectures. This change
fixes the issue by forcing 64bit computation during frequency
to counter conversion.

core: correct time conversion in delay support

The previous code may overflow in 32bit architectures. This change
fixes the issue by forcing 64bit computation during frequency
to counter conversion.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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706c2c7028-Sep-2018 Sumit Garg <sumit.garg@linaro.org>

thread: fix stack space to not be part of tee.bin

Commit 935364080364 ("thread: move stacks to separate sections") makes
stack space to be part of tee.bin which leads to approx. 130K increase
in siz

thread: fix stack space to not be part of tee.bin

Commit 935364080364 ("thread: move stacks to separate sections") makes
stack space to be part of tee.bin which leads to approx. 130K increase
in size of tee.bin for platform with 2 threads.
So this patch fixes the stack space to be in NOLOAD section only.

Fixes: 935364080364 ("thread: move stacks to separate sections")
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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8e01b4b903-Oct-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: arm32: fix saving vfp state

Prior to this patch TF-A in AArch32 didn't save the normal world VFP
data registers and thus always restored then as zeroes and causing
problems in normal world.

W

core: arm32: fix saving vfp state

Prior to this patch TF-A in AArch32 didn't save the normal world VFP
data registers and thus always restored then as zeroes and causing
problems in normal world.

With this patch if running with TF-A in AArch32 save the VFP state using
the same logic as in AArch64. Since TF-A saves and restores CPACR_EL1 we
cannot tell if normal world currently is using VFP or not so we have to
assume that it is and always save the VFP data registers if they are
about to be changed.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey AArch32)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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d7ef633401-Oct-2018 Etienne Carriere <etienne.carriere@linaro.org>

core: user_ta: set freed EXIDX pointer to NULL

Clear reference of user TA exception index table once it
is freed, otherwise it is freed a second time. This
issue occurs when set_exidx() fails for so

core: user_ta: set freed EXIDX pointer to NULL

Clear reference of user TA exception index table once it
is freed, otherwise it is freed a second time. This
issue occurs when set_exidx() fails for some reasons as
an out of memory issue. This change prevents core from
panicking when it occurs.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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1cccb13f26-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: default guard reg_shm mobjs

Add a special guard for registered shared memory MOBJs to make sure that
it's not possible to release MOBJs which aren't created by an explicit
registration from no

core: default guard reg_shm mobjs

Add a special guard for registered shared memory MOBJs to make sure that
it's not possible to release MOBJs which aren't created by an explicit
registration from normal world.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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c0e7f04e26-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: mobj_reg_shm_free() using mobj_reg_shm_put()

Let reg_shm MOBJs be completely reference counted meaning that
mobj_free() on a reg_shm MOBJ only decrease the reference counter and
only free it i

core: mobj_reg_shm_free() using mobj_reg_shm_put()

Let reg_shm MOBJs be completely reference counted meaning that
mobj_free() on a reg_shm MOBJ only decrease the reference counter and
only free it if it reaches 0.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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f3a01e3a26-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: remove mobj_reg_shm_{,un}map()

Removes mobj_reg_shm_map() and mobj_reg_shm_unmap(), they are replaced
by mobj_reg_shm_inc_map() and mobj_reg_shm_dec_map().

Reviewed-by: Etienne Carriere <etie

core: remove mobj_reg_shm_{,un}map()

Removes mobj_reg_shm_map() and mobj_reg_shm_unmap(), they are replaced
by mobj_reg_shm_inc_map() and mobj_reg_shm_dec_map().

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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2dd4367c26-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: pta: use mobj_reg_shm_{inc,dec}_map()

Use mobj_reg_shm_inc_map() and mobj_reg_shm_dec_map() instead of
mobj_reg_shm_map() and mobj_reg_shm_unmap().

Acked-by: Etienne Carriere <etienne.carrier

core: pta: use mobj_reg_shm_{inc,dec}_map()

Use mobj_reg_shm_inc_map() and mobj_reg_shm_dec_map() instead of
mobj_reg_shm_map() and mobj_reg_shm_unmap().

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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162f445426-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: add mobj_reg_shm_{inc,dec}_map()

mobj_reg_shm_inc_map() used when a reg_shm mobj needs to be mapped and
mobj_reg_shm_dec_map() is called when the mapping isn't needed any
longer.

Reviewed-by:

core: add mobj_reg_shm_{inc,dec}_map()

mobj_reg_shm_inc_map() used when a reg_shm mobj needs to be mapped and
mobj_reg_shm_dec_map() is called when the mapping isn't needed any
longer.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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0b020f9426-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: remove reg_shm_{put,free}_by_cookie()

Removes the two functions mobj_reg_shm_put_by_cookie() and
mobj_reg_shm_free_by_cookie(). mobj_reg_shm_put() and mobj_free() should
be used instead.

Revi

core: remove reg_shm_{put,free}_by_cookie()

Removes the two functions mobj_reg_shm_put_by_cookie() and
mobj_reg_shm_free_by_cookie(). mobj_reg_shm_put() and mobj_free() should
be used instead.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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46b3233726-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: entry_std: free/put by mobj in call cleanup

Use the mobj pointer instead of a shm_ref when cleaning up parameters
in cleanup_shm_refs() at the end of a call.

Reviewed-by: Etienne Carriere <e

core: entry_std: free/put by mobj in call cleanup

Use the mobj pointer instead of a shm_ref when cleaning up parameters
in cleanup_shm_refs() at the end of a call.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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8b0c136726-Sep-2018 Jens Wiklander <jens.wiklander@linaro.org>

core: add mobj_reg_shm_put()

Adds mobj_reg_shm_put() for reference counting without cookie.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander

core: add mobj_reg_shm_put()

Adds mobj_reg_shm_put() for reference counting without cookie.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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09614f8e01-Oct-2018 Etienne Carriere <etienne.carriere@linaro.org>

core: correct memory layout trace

Buffers that end at end of the available address range which
may happen on 32bit machine fail have an end address that of
computed as 0. This change uses a 64bit ad

core: correct memory layout trace

Buffers that end at end of the available address range which
may happen on 32bit machine fail have an end address that of
computed as 0. This change uses a 64bit address computation
to prevent the displayed end address being 0.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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385000b001-Oct-2018 Etienne Carriere <etienne.carriere@linaro.org>

core: correct overflows in range overlap functions

Buffers that end at end of the available address range which
may happen on 32bit machine fail have an end address that of
computed as 0. This chang

core: correct overflows in range overlap functions

Buffers that end at end of the available address range which
may happen on 32bit machine fail have an end address that of
computed as 0. This change uses the computation already used
in _core_is_buffer_inside() to ensure functions
_core_is_buffer_outside() and _core_is_buffer_intersect()
return a reliable result.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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