core: base memory registration on scatter array

The register_*() macros are now implemented using scatter array.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissi

core: base memory registration on scatter array

The register_*() macros are now implemented using scatter array.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: base pseudo_ta_register() on scatter array

The pseudo_ta_register() implementation is now based on scatter array.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome

core: base pseudo_ta_register() on scatter array

The pseudo_ta_register() implementation is now based on scatter array.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: initcall.h use scattered array

Initcalls uses generic scattered array instead of special
implementation.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier

core: initcall.h use scattered array

Initcalls uses generic scattered array instead of special
implementation.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add scattered array

Adds a scattered array which allows defining arrays scattered over
several source files. The implementation is based on some support by the
linker.

This is a generic solut

core: add scattered array

Adds a scattered array which allows defining arrays scattered over
several source files. The implementation is based on some support by the
linker.

This is a generic solution to initcalls and other similar scattered
initializations.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: keep.h: avoid duplicate symbols

Prior to this patch if the KEEP_*() macros are used with two static
variables with the same name but in different source files it will
result in a duplicated gl

core: keep.h: avoid duplicate symbols

Prior to this patch if the KEEP_*() macros are used with two static
variables with the same name but in different source files it will
result in a duplicated global symbol. This happens because the internal
trickery uses global variables based on the static symbol it's supposed
to keep. With this patch the global variables uses the file unique
define __FILE_ID__ to avoid the conflict.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: asan: support GCC version >= 7.0

With GCC 7.0 there was an ABI change for the address sanitizer. This
patch extends struct asan_global with the new odr_indicator field to
work with this new AB

core: asan: support GCC version >= 7.0

With GCC 7.0 there was an ABI change for the address sanitizer. This
patch extends struct asan_global with the new odr_indicator field to
work with this new ABI.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: embedded secure device tree

This change introduces configurations CFG_EMDED_DTB and
CFG_EMBED_DTB_SOURCE_FILE. When CFG_EMDED_DTB=y a device
tree blob (DTB) is embedded in a read-only section

core: embedded secure device tree

This change introduces configurations CFG_EMDED_DTB and
CFG_EMBED_DTB_SOURCE_FILE. When CFG_EMDED_DTB=y a device
tree blob (DTB) is embedded in a read-only section of the
core based on an in-tree device tree source (DTS) file.

CFG_EMBED_DTS_SOURCE_FILE defines the relative path of
the target device in core/arch/$(ARCH)/dts.

Non empty CFG_EMBED_DTS_SOURCE_FILE content implies CFG_EMBED_DTB=y.
CFG_EMBED_DTB=y mandates CFG_EMBED_DTS_SOURCE_FILE definition.
CFG_EMDED_DTB=y mandates CFG_DT=y.

Since the embedded DTB is read-only, core do not attempt to
modify it adding information such as OP-TEE resources nodes and
properties. Core still get generic information such as system
memory address range and debug console configuration
from the embedded DTB.

Documentation includes a DT section in the OP-TEE design
description.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix bug in vm_map() causing pager panic()

Prior to this patch vm_map() didn't allocate new page tables (PGTs) as
needed, it only checked that it later would be possible to allocate the
needed

core: fix bug in vm_map() causing pager panic()

Prior to this patch vm_map() didn't allocate new page tables (PGTs) as
needed, it only checked that it later would be possible to allocate the
needed PGTs. This is enough if the user_ta_ctx (UTC) isn't active. With
dynamically linked libraries the UTC will be active when vm_map() is
called to make room for the new segments. If the already allocated PGTs
happen to cover even the new memory range it will still work, this is
normally the case with CFG_WITH_LPAE=y since each page table covers 2
MiB. With CFG_WITH_LPAE=n the page tables only covers 1 MiB and that's
not enough when loading the os_test TA in xtest case 1006.

This patch fixes the problem by instead of just checking that it later
will be possible to allocate needed PGTs, it also allocates the PGTs if
the UTC is active.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove MOBJ_INVALID_COOKIE

Removes MOBJ_INVALID_COOKIE which resulted in an unexpected ABI change
against the normal world driver. Instead 0 is continued to be used as an
invalid/absent cookie

core: remove MOBJ_INVALID_COOKIE

Removes MOBJ_INVALID_COOKIE which resulted in an unexpected ABI change
against the normal world driver. Instead 0 is continued to be used as an
invalid/absent cookie value.

Tested-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Sumit Garg <sumit.garg@linaro.org>
Fixes: cd278f78382b ("core: simplify shm cookie handling")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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zlib: fix compiler warning

GCC 8.x warns when building core/lib/zlib/inflate.c:

$ make PLATFORM=hikey-hikey960 out/arm-plat-hikey/core/lib/zlib/inflate.o
[...]
core/lib/zlib/inflate.c: In functi

zlib: fix compiler warning

GCC 8.x warns when building core/lib/zlib/inflate.c:

$ make PLATFORM=hikey-hikey960 out/arm-plat-hikey/core/lib/zlib/inflate.o
[...]
core/lib/zlib/inflate.c: In function ‘inflate’:
core/lib/zlib/inflate.c:842:25: warning: this statement may fall through [-Wimplicit-fallthrough=]
state->mode = DICT;
~~~~~~~~~~~~^~~~~~
core/lib/zlib/inflate.c:843:9: note: here
case DICT:
^~~~
[...]

Fix that by adding some /* Fall through */ comments.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto: add TEE_ALG_RSASSA_PKCS1_V1_5

This change integrates the LTC_PKCS_1_V1_5_NA1 into OPTEE as an
extension as TEE_ALG_RSASSA_PKCS1_V1_5. This scheme allows to do
PKCS#1 v1.5 EMSA without

core: crypto: add TEE_ALG_RSASSA_PKCS1_V1_5

This change integrates the LTC_PKCS_1_V1_5_NA1 into OPTEE as an
extension as TEE_ALG_RSASSA_PKCS1_V1_5. This scheme allows to do
PKCS#1 v1.5 EMSA without ASN.1 around the hash. It is used for
implementing the pkcs#11 CKM_RSA_PKCS mechanism for signing and
verifying in SKS.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Gabor Szekely <szvgabor@gmail.com>

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libtomcrypt: port LTC_PKCS_1_V1_5_NA1 from ltc v1.18.2

This change ports LTC_PKCS_1_V1_5_NA1 from libtomcrypt v1.18.2. This
scheme allows to do PKCS#1 v1.5 EMSA without ASN.1 around the hash. It
is

libtomcrypt: port LTC_PKCS_1_V1_5_NA1 from ltc v1.18.2

This change ports LTC_PKCS_1_V1_5_NA1 from libtomcrypt v1.18.2. This
scheme allows to do PKCS#1 v1.5 EMSA without ASN.1 around the hash. It
is used for implementing the pkcs#11 CKM_RSA_PKCS mechanism for signing
and verifying in SKS. This commit is a cherry pick of aa4bae5ae9a2 from
the libtomcrypt repository.

Link: <https://github.com/libtom/libtomcrypt/commit/aa4bae5ae9a2>

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Gabor Szekely <szvgabor@gmail.com>

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core: introduce generic optee_rpc_cmd.h

Replaces the OPTEE_MSG RPC command protocol descriptions in optee_msg.h
and optee_msg_supplicant with a generic optee_rpc_cmd.h. Defined names
are also refact

core: introduce generic optee_rpc_cmd.h

Replaces the OPTEE_MSG RPC command protocol descriptions in optee_msg.h
and optee_msg_supplicant with a generic optee_rpc_cmd.h. Defined names
are also refactored to mirror the new structure.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pta/gprof.c: get rid of init_memparam()

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens

core: pta/gprof.c: get rid of init_memparam()

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: tadb.c: get rid of init_memparam()

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wikl

core: tadb.c: get rid of init_memparam()

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: tee_fs_rpc.c get rid of init_memparam()

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens

core: tee_fs_rpc.c get rid of init_memparam()

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pta_socket.c: simplify struct thread_param

Simplify struct thread_param usage in PTA socket with direct
initialization.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jero

core: pta_socket.c: simplify struct thread_param

Simplify struct thread_param usage in PTA socket with direct
initialization.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: msg_param: remove unused functions

Removes the unused functions msg_param_init_memparam() and
msg_param_get_buf_size().

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jero

core: msg_param: remove unused functions

Removes the unused functions msg_param_init_memparam() and
msg_param_get_buf_size().

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: use struct thread_param for RPC

Use struct thread_param as an abstraction of the parameters used for
RPC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <

core: use struct thread_param for RPC

Use struct thread_param as an abstraction of the parameters used for
RPC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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LTC: drop LTC_NO_ASM and configure

Drops LTC_NO_ASM and configures endian and word size accordingly, that
is, little endian and 32-bit or 64-bit depending on arm architecture.

Defines ulong32 and u

LTC: drop LTC_NO_ASM and configure

Drops LTC_NO_ASM and configures endian and word size accordingly, that
is, little endian and 32-bit or 64-bit depending on arm architecture.

Defines ulong32 and ulong64 based on uint32_t and uint64_t to make
sure that the types are always defined correctly.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: switch to mbedtls for bignum

Adds a mpi_desc.c wrapper to LTC in order to enable usage of bignum
(mpi) routines from mbedtls.

CFG_MBEDTLS_MPI=y (default y) builds the bignum routines for mbed

core: switch to mbedtls for bignum

Adds a mpi_desc.c wrapper to LTC in order to enable usage of bignum
(mpi) routines from mbedtls.

CFG_MBEDTLS_MPI=y (default y) builds the bignum routines for mbedtls and
also enables their usage in LTC and by that replaces libmpa for
privileged mode usage.

User mode TAs still use libmpa.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Move __early_ta from <compiler.h> to <kernel/early_ta.h>

The __early_ta macro is used only in C files generated by
scripts/ta_bin_to_c.py. There is no reason to have it defined in a widely
used head

Move __early_ta from <compiler.h> to <kernel/early_ta.h>

The __early_ta macro is used only in C files generated by
scripts/ta_bin_to_c.py. There is no reason to have it defined in a widely
used header like <compiler.h>.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: force read-only flag on .rodata.* sections

This commit fixes a warning with GCC 8.2 that did not occur with GCC 6.2:

$ make out/arm-plat-vexpress/core/arch/arm/kernel/user_ta.o
CHK ou

core: force read-only flag on .rodata.* sections

This commit fixes a warning with GCC 8.2 that did not occur with GCC 6.2:

$ make out/arm-plat-vexpress/core/arch/arm/kernel/user_ta.o
CHK out/arm-plat-vexpress/conf.mk
CHK out/arm-plat-vexpress/include/generated/conf.h
CHK out/arm-plat-vexpress/core/include/generated/asm-defines.h
CC out/arm-plat-vexpress/core/arch/arm/kernel/user_ta.o
{standard input}: Assembler messages:
{standard input}:4087: Warning: setting incorrect section attributes for .rodata.__unpaged

The message is printed as the assembler processes this code fragment,
generated by the C compiler:

.section .rodata.__unpaged,"aw"

The older compiler (GCC 6.2) would generate instead:

.section .rodata.__unpaged,"a",%progbits

The problem with .rodata.__unpaged,"aw" is that the "w" (writeable) flag
is not consistent with the section name (.rodata.*), which by convention
is supposed to be read-only.

- The section name (".rodata.__unpaged") is given by our macro:
__rodata_unpaged.
- The "w" flag is added by GCC, not sure why exactly. One reason [1] is
when a relocatable binary is being generated and the structure contains
relocatable data. But, we are not explicitly asking for a relocatable
binary, so this might as well be a bug or counter-intuitive feature of
the compiler.

Anyway, to avoid the warning, we need to fix the section flags. The
section type (%progbits) is optional, it is deduced from the section name
by default. %progbits indicates that the section contains data (i.e., is
not empty).

Link: [1] https://gcc.gnu.org/ml/gcc/2004-05/msg01016.html
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960)
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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libfdt: Move to version v1.4.6-9

This import adds FDT overlay plus brings in the latest bugfixes upstream.

As noted in the below url, there is a performance problem with 1.4.7 so we
target version

libfdt: Move to version v1.4.6-9

This import adds FDT overlay plus brings in the latest bugfixes upstream.

As noted in the below url, there is a performance problem with 1.4.7 so we
target version 1.4.6-9 instead.

https://github.com/ARM-software/arm-trusted-firmware/pull/1657

Upstream commit aadd0b65c987 ("checks: centralize printing of property
names in failure messages")

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: GICv3: Handle group 1 secure interrupts

As per GICv3 architecture specification (Section 4.6 Interrupt grouping),
secure EL1 (Trusted OS) handles secure group 1 physical interrupts and
EL3

drivers: GICv3: Handle group 1 secure interrupts

As per GICv3 architecture specification (Section 4.6 Interrupt grouping),
secure EL1 (Trusted OS) handles secure group 1 physical interrupts and
EL3 handles group 0 physical interrupts which are considered as FIQs
(foreign interrupt) for Trusted OS.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (FVP)
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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