drivers/scmi-msg: driver for processing scmi messages

This change introduces drivers to allow a platform to create a SCMI
service and register handlers for client request (SCMI agent) on
system reso

drivers/scmi-msg: driver for processing scmi messages

This change introduces drivers to allow a platform to create a SCMI
service and register handlers for client request (SCMI agent) on
system resources. This is the first piece of the drivers: an entry
function, the SCMI base protocol support and helpers for create
the response message.

With this change, scmi_process_message() is the entry function to
process an incoming SCMI message. The function expect the message
is already copied from shared memory into secure memory. The message
structure stores message reference and output buffer reference where
response message shall be stored.

scmi_process_message() calls the SCMI protocol driver according to
the protocol ID in the message. The SCMI protocol driver will call
defined platform handlers according to the message content.

This change introduces only the SCMI base protocol as defined in
SCMI specification v2.0 [1]. Not all the messages defined
in the specification are supported.

SCMI resource in this implementation are dumped or inspired by the
SCP-firmware implementation [2] of the SCMI protocol, server side.

Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
Link: [2] https://github.com/ARM-software/SCP-firmware.git

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: TEE capability for null sized memrefs support

Introduce a new capability OPTEE_SMC_SEC_CAP_MEMREF_NULL to reflect
support for null shared memory references that is buffer references
with null

core: TEE capability for null sized memrefs support

Introduce a new capability OPTEE_SMC_SEC_CAP_MEMREF_NULL to reflect
support for null shared memory references that is buffer references
with null size and null address reference.

Signed-off-by: Michael Whitfield <michael.whitfield@nxp.com>
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Joakim Bech <joakim.bech@linaro.org> (QEMU)

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core: merge tee_*_get_digest_size() into a single function

Rename tee_hash_get_digest_size() to tee_alg_get_digest_size().

Change tee_alg_get_digest_size() to use new libutee macro
TEE_ALG_GET_DIGE

core: merge tee_*_get_digest_size() into a single function

Rename tee_hash_get_digest_size() to tee_alg_get_digest_size().

Change tee_alg_get_digest_size() to use new libutee macro
TEE_ALG_GET_DIGEST_SIZE.

Remove tee_mac_get_digest_size() as its functionality
is handled by tee_alg_get_digest_size() now.

Signed-off-by: Albert Schwarzkopf <a.schwarzkopf@phytec.de>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: clock: allow tree lookup for several system clocks

Oscillators, PLLs and some system clocks can be related straight to
a parent clock identifier. Prior this change were only oscillato

plat-stm32mp1: clock: allow tree lookup for several system clocks

Oscillators, PLLs and some system clocks can be related straight to
a parent clock identifier. Prior this change were only oscillators
and few clocks supported by this look up scheme. This changes makes all
parent IDs covered supported. This enables for flexible use of clock
tree exploration when computing a clock frequency value.

Introduces helper function clock_id2parent_id() for clock ID
to parent ID conversion and defines helper right above parent clock
resources for consistency.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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plat-stm32mp1: allow fdt to disable root clocks

Assign a null frequency value to root clocks when FDT defines them
as disabled.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: R

plat-stm32mp1: allow fdt to disable root clocks

Assign a null frequency value to root clocks when FDT defines them
as disabled.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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plat-stm32mp1: clock: handle always-on clocks

Oscillators, PLLs and AXI/MPU/MCU clocks are not gated from
functions stm32_clock_enable() and stm32_clock_disable(). This change
allows these functions

plat-stm32mp1: clock: handle always-on clocks

Oscillators, PLLs and AXI/MPU/MCU clocks are not gated from
functions stm32_clock_enable() and stm32_clock_disable(). This change
allows these functions and stm32_clock_is_enabled() to blindly handle
clock gating for such always-on clocks. Gating these clocks is out of
the scope of this change even if preferred for power consumption
optimization considerations.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove '.section .text.<name>' and use function macros instead

Assembler functions are normally defined using the FUNC/LOCAL_FUNC
macros from <asm.S>. The macros takes care of several things, includ

Remove '.section .text.<name>' and use function macros instead

Assembler functions are normally defined using the FUNC/LOCAL_FUNC
macros from <asm.S>. The macros takes care of several things, including
putting the function in a specific section for later garbage collection
by the linker (--gc-sections).

A few files do not follow this convention, let's fix them. Two
functions in ghash-ce-core_a64.S (pmull_gcm_load_round_keys() and
pmull_gcm_aes_sub()) totally lack a .section directive, which I think
is a mistake. Fix them at the same time.

No functional change is expected.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: clock: don't embed unused non-secure uart clocks

Embed UART parent clock resource upon CFG_WITH_NSEC_UARTS=y.
This configuration switch was already used to embed or not
the non-secure

plat-stm32mp1: clock: don't embed unused non-secure uart clocks

Embed UART parent clock resource upon CFG_WITH_NSEC_UARTS=y.
This configuration switch was already used to embed or not
the non-secure UART clocks but not the resources used to
look for their parent clock.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: remove unused usb non-secure clock

Remove unused clocks USBO_CLK and USBPHY_K resources.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@

plat-stm32mp1: remove unused usb non-secure clock

Remove unused clocks USBO_CLK and USBPHY_K resources.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: add mdma secure clock

Add support for MDMA secure clock.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

plat-stm32mp1: clock: add rtc as gateable clock

Add support for RTC clock.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

plat-stm32mp1: clock: fix mcu/axi parent clock

Correct MCU clock parent selector: MCU subsystem clock is derived
from clock PLL3_P, not PLL3.

Correct AXI clock parent selector: AXI subsystem clock

plat-stm32mp1: clock: fix mcu/axi parent clock

Correct MCU clock parent selector: MCU subsystem clock is derived
from clock PLL3_P, not PLL3.

Correct AXI clock parent selector: AXI subsystem clock is derived
from clock PLL2_P, not PLL2.

This change also renames MCU clock and AXI clock resources to
prevent confusion.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: clock: remove oscillators and PLLs from shared resources

In stm32mp1 SoCs, oscillators, PLL1 and PLL2 are not resources allocated
at runtime upon platform configuration in OP-TEE. The

plat-stm32mp1: clock: remove oscillators and PLLs from shared resources

In stm32mp1 SoCs, oscillators, PLL1 and PLL2 are not resources allocated
at runtime upon platform configuration in OP-TEE. These are always
considered under secure world control. This change removes them from the
list of the shared resources.

Update function stm32mp_register_clock_parents_secure() accordingly.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers/stm32_rng: register device as secure or non-secure

FDT data defines through the status/secure-status property whether
RNG device is assigned to the secure world or to the non-secure
world. T

drivers/stm32_rng: register device as secure or non-secure

FDT data defines through the status/secure-status property whether
RNG device is assigned to the secure world or to the non-secure
world. This change makes the device driver to register the
peripheral assignation at boot time.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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drivers/stm32_etzpc: fix tzma configuration

Correct TZMAs configuration restore sequence at PM resume.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Rouven Czerwinski <r.czerw

drivers/stm32_etzpc: fix tzma configuration

Correct TZMAs configuration restore sequence at PM resume.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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core: check writeable in tee_svc_copy_param()

Check that the callee_params are writeable too in tee_svc_copy_param()
as they will be updated in tee_svc_update_out_param() in case one of the
paramete

core: check writeable in tee_svc_copy_param()

Check that the callee_params are writeable too in tee_svc_copy_param()
as they will be updated in tee_svc_update_out_param() in case one of the
parameters is an "out" parameter. To keep it simple always require
callee_params to be writeable.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reported-by: Bastien Simondi <bsimondi@netflix.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: fix function for rpmb ready check

This was not caught by me during the rebase and not caught by CI because
we don't build any imx platform with CFG_RPMB_FS=y.

Reported-by: Jorge Ramirez-

core: imx: fix function for rpmb ready check

This was not caught by me during the rebase and not caught by CI because
we don't build any imx platform with CFG_RPMB_FS=y.

Reported-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Jerome Forissier <jerome@forissier.org>

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rpmb: fix call to plat_rpmb_key_is_ready()

In tee_rpmb_write_and_verify_key() a call was recently added to check if
the RPMB key was ready to be retrieved. But the function wasn't called
in the new

rpmb: fix call to plat_rpmb_key_is_ready()

In tee_rpmb_write_and_verify_key() a call was recently added to check if
the RPMB key was ready to be retrieved. But the function wasn't called
in the new if statement, instead was just the address of the function
tested to be non-NULL. So with this patch add the missing () to make it
a function call.

Fixes: b1042535dc3e ("rpmb: function to block rpmb write per platform")
Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: change reset functions to get a timeout argument

Stm32mp1 reset function APIs now get a timeout argument and return
an error if reset domain has not effectively reset when timeout has

plat-stm32mp1: change reset functions to get a timeout argument

Stm32mp1 reset function APIs now get a timeout argument and return
an error if reset domain has not effectively reset when timeout has
expired. A null timeout means the driver loads target reset state
and return without waiting request domain reset state is reached.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: get shared reset controller state

stm32mp_nsec_can_access_reset() tells whether a reset controller
is assigned to the secure world only, or when it can be manipulated
by the non-secur

plat-stm32mp1: get shared reset controller state

stm32mp_nsec_can_access_reset() tells whether a reset controller
is assigned to the secure world only, or when it can be manipulated
by the non-secure world.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: define memory dma to shared resource

This change defines memory DMA as a shared resource. Despite
Secure and non-secure have have specific access to memory
DMA, the reset control is e

plat-stm32mp1: define memory dma to shared resource

This change defines memory DMA as a shared resource. Despite
Secure and non-secure have have specific access to memory
DMA, the reset control is exclusive to the secure world.

With memory DMAs defined as the shared resource, the secure
world will be able to open access to the resource if it is
not used by the secure side.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add TEE_LOGIN_REE_KERNEL login method

Add private login method for REE kernel clients to invoke TAs. It allows
a TA to distinguish among normal world clients whether its a REE kernel
client or

core: add TEE_LOGIN_REE_KERNEL login method

Add private login method for REE kernel clients to invoke TAs. It allows
a TA to distinguish among normal world clients whether its a REE kernel
client or a REE user-space client.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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drivers: gic: allow set pending a non-secure SGI

Remove assertion in GIC driver function gic_it_set_pending()
preventing Core from setting as pending a non-secure SGI.

Reviewed-by: Etienne Carriere

drivers: gic: allow set pending a non-secure SGI

Remove assertion in GIC driver function gic_it_set_pending()
preventing Core from setting as pending a non-secure SGI.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>

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drivers/stm32_etzpc: initialize etzpc driver early

Changes initcall level for STM32 ETZPC driver so that in initializes
early, at service_init level. The driver does not depends on other
SoC drivers

drivers/stm32_etzpc: initialize etzpc driver early

Changes initcall level for STM32 ETZPC driver so that in initializes
early, at service_init level. The driver does not depends on other
SoC drivers and can be initialize early. This change allows other
driver_init level initialization sequence to use ETZPC resources.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: implement NXP CAAM driver - Cipher

Add the NXP CAAM drivers:
- Cipher (AES/DES/DES3)

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faur

drivers: caam: implement NXP CAAM driver - Cipher

Add the NXP CAAM drivers:
- Cipher (AES/DES/DES3)

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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