xref: /optee_os/core/arch/arm/plat-stm32mp1/conf.mk (revision d9c569c9c765ed6f0fe6e131d1a33c9c32c0ba08)
1PLATFORM_FLAVOR ?= stm32mp157
2
3# 1GB and 512MB DDR target do not locate secure DDR at the same place.
4#
5flavorlist-1G = stm32mp157c-ev1.dts stm32mp157c-ed1.dts
6flavorlist-512M = stm32mp157c-dk2.dts
7
8include core/arch/arm/cpu/cortex-a7.mk
9
10$(call force,CFG_BOOT_SECONDARY_REQUEST,y)
11$(call force,CFG_GENERIC_BOOT,y)
12$(call force,CFG_GIC,y)
13$(call force,CFG_INIT_CNTVOFF,y)
14$(call force,CFG_PM_STUBS,y)
15$(call force,CFG_PSCI_ARM32,y)
16$(call force,CFG_SECONDARY_INIT_CNTFRQ,y)
17$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
18$(call force,CFG_SM_PLATFORM_HANDLER,y)
19$(call force,CFG_WITH_SOFTWARE_PRNG,y)
20
21ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),)
22CFG_TZDRAM_START ?= 0xde000000
23CFG_SHMEM_START  ?= 0xdfe00000
24CFG_DRAM_SIZE    ?= 0x20000000
25endif
26
27CFG_TZSRAM_START ?= 0x2ffc0000
28CFG_TZSRAM_SIZE  ?= 0x0003f000
29CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000
30CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000
31CFG_TZDRAM_START ?= 0xfe000000
32CFG_TZDRAM_SIZE  ?= 0x01e00000
33CFG_SHMEM_START  ?= 0xffe00000
34CFG_SHMEM_SIZE   ?= 0x00200000
35CFG_DRAM_SIZE    ?= 0x40000000
36
37CFG_TEE_CORE_NB_CORE ?= 2
38CFG_WITH_PAGER ?= y
39CFG_WITH_LPAE ?= y
40CFG_WITH_STACK_CANARIES ?= y
41CFG_MMAP_REGIONS ?= 23
42
43ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),)
44# Some drivers mandate DT support
45$(call force,CFG_STM32_I2C,n)
46endif
47
48CFG_STM32_BSEC ?= y
49CFG_STM32_ETZPC ?= y
50CFG_STM32_GPIO ?= y
51CFG_STM32_I2C ?= y
52CFG_STM32_RNG ?= y
53CFG_STM32_RNG ?= y
54CFG_STM32_UART ?= y
55
56# Default enable some test facitilites
57CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y
58CFG_WITH_STATS ?= y
59
60# Non-secure UART and GPIO/pinctrl for the output console
61CFG_WITH_NSEC_GPIOS ?= y
62CFG_WITH_NSEC_UARTS ?= y
63# UART instance used for early console (0 disables early console)
64CFG_STM32_EARLY_CONSOLE_UART ?= 4
65