xref: /optee_os/core/arch/arm/plat-stm32mp1/conf.mk (revision 8fa3e895ff00f06f6666a9dfa0affaa3451775cf)
1PLATFORM_FLAVOR ?= stm32mp157
2
3# 1GB and 512MB DDR target do not locate secure DDR at the same place.
4#
5flavorlist-1G = stm32mp157c-ev1.dts stm32mp157c-ed1.dts
6flavorlist-512M = stm32mp157c-dk2.dts
7
8include core/arch/arm/cpu/cortex-a7.mk
9
10$(call force,CFG_BOOT_SECONDARY_REQUEST,y)
11$(call force,CFG_GENERIC_BOOT,y)
12$(call force,CFG_GIC,y)
13$(call force,CFG_INIT_CNTVOFF,y)
14$(call force,CFG_PM_STUBS,y)
15$(call force,CFG_PSCI_ARM32,y)
16$(call force,CFG_SCMI_MSG_DRIVERS,y)
17$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y)
18$(call force,CFG_SCMI_MSG_SMT,y)
19$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y)
20$(call force,CFG_SECONDARY_INIT_CNTFRQ,y)
21$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
22$(call force,CFG_SM_PLATFORM_HANDLER,y)
23$(call force,CFG_WITH_SOFTWARE_PRNG,y)
24
25ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),)
26CFG_TZDRAM_START ?= 0xde000000
27CFG_SHMEM_START  ?= 0xdfe00000
28CFG_DRAM_SIZE    ?= 0x20000000
29endif
30
31CFG_TZSRAM_START ?= 0x2ffc0000
32CFG_TZSRAM_SIZE  ?= 0x0003f000
33CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000
34CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000
35CFG_TZDRAM_START ?= 0xfe000000
36CFG_TZDRAM_SIZE  ?= 0x01e00000
37CFG_SHMEM_START  ?= 0xffe00000
38CFG_SHMEM_SIZE   ?= 0x00200000
39CFG_DRAM_SIZE    ?= 0x40000000
40
41CFG_TEE_CORE_NB_CORE ?= 2
42CFG_WITH_PAGER ?= y
43CFG_WITH_LPAE ?= y
44CFG_WITH_STACK_CANARIES ?= y
45CFG_MMAP_REGIONS ?= 23
46
47ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),)
48# Some drivers mandate DT support
49$(call force,CFG_STM32_I2C,n)
50endif
51
52CFG_STM32_BSEC ?= y
53CFG_STM32_ETZPC ?= y
54CFG_STM32_GPIO ?= y
55CFG_STM32_I2C ?= y
56CFG_STM32_RNG ?= y
57CFG_STM32_RNG ?= y
58CFG_STM32_UART ?= y
59
60# Default enable some test facitilites
61CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y
62CFG_WITH_STATS ?= y
63
64# Default disable some support for pager memory size constraint
65CFG_TEE_CORE_DEBUG ?= n
66CFG_UNWIND ?= n
67CFG_LOCKDEP ?= n
68CFG_CORE_ASLR ?= n
69
70# Non-secure UART and GPIO/pinctrl for the output console
71CFG_WITH_NSEC_GPIOS ?= y
72CFG_WITH_NSEC_UARTS ?= y
73# UART instance used for early console (0 disables early console)
74CFG_STM32_EARLY_CONSOLE_UART ?= 4
75