rpmb: fix building when TRACE_LEVEL >= TRACE_FLOW

Building with CFG_RPMB_FS=y and CFG_TEE_CORE_LOG_LEVEL=4 yields a
compile-time error due to a typo.

Replacing TEE_RESULT with TEE_Result fixes the

rpmb: fix building when TRACE_LEVEL >= TRACE_FLOW

Building with CFG_RPMB_FS=y and CFG_TEE_CORE_LOG_LEVEL=4 yields a
compile-time error due to a typo.

Replacing TEE_RESULT with TEE_Result fixes the issue.

Signed-off-by: Gianguido Sorà <me@gsora.xyz>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

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plat-hisilicon: psci: support Arm SMCCC_VERSION function ID

As per Arm SMCCC v1.1 specification [1], PSCI PSCI_FEATURES function ID
should report Arm Architecture Call SMCCC_VERSION as supported whe

plat-hisilicon: psci: support Arm SMCCC_VERSION function ID

As per Arm SMCCC v1.1 specification [1], PSCI PSCI_FEATURES function ID
should report Arm Architecture Call SMCCC_VERSION as supported when
the secure firmware supports both PSCI PSCI_FEATURES function ID and
Arm SMCCC_VERSION function ID.

Link: [1] https://developer.arm.com/docs/den0028/latest
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: SiP SMC service for BSEC access

Implement a SiP SMC based interface fàr the non-secure world to access
BSEC words. The service is embedded upon CFG_STM32_BSEC_SIP=y. If not
embedded,

plat-stm32mp1: SiP SMC service for BSEC access

Implement a SiP SMC based interface fàr the non-secure world to access
BSEC words. The service is embedded upon CFG_STM32_BSEC_SIP=y. If not
embedded, the service simply reports a failure.

This service is used by U-boot package since its release v2019.07-rc1 [1]
to retrieve information such as the device MAC address [2].

Link: [1] https://github.com/u-boot/u-boot/blob/v2019.07-rc1/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h
Link: [2] https://github.com/u-boot/u-boot/blob/v2019.07-rc1/arch/arm/mach-stm32mp/cpu.c#L475

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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dts: stm32mp1: non-secure can access MAC address and board ID OTPs

Add property st,non-secure-otp to MAC address NVMEM cells in stm32mp1
SoC DTSI and to board ID NVMEM cells in stm32mp1 ST boards DT

dts: stm32mp1: non-secure can access MAC address and board ID OTPs

Add property st,non-secure-otp to MAC address NVMEM cells in stm32mp1
SoC DTSI and to board ID NVMEM cells in stm32mp1 ST boards DTS files
since non-secure world is allowed to access these OTPs despite they
are located in the upper BSEC words (secure) area.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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stm32_bsec: grant BSEC words non-secure access from embedded DTB

Change BSEC driver to allow non-secure world to access specific BSEC
upper words that have the ST NVMEM property "st,non-secure-otp".

stm32_bsec: grant BSEC words non-secure access from embedded DTB

Change BSEC driver to allow non-secure world to access specific BSEC
upper words that have the ST NVMEM property "st,non-secure-otp". The
property is presented to the LKML in [1].

During BSEC driver initialization, a bit fields array is allocated to
store whether each 32bit BSEC upper words is allowed to be accessed by
the non-secure world.

Link: [1] https://lkml.org/lkml/2020/5/8/1258
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: psci: support Arm SMCCC_VERSION function ID

As per Arm SMCCC v1.1 specification [1], PSCI PSCI_FEATURES function ID
should report Arm Architecture Call SMCCC_VERSION as supported when

plat-stm32mp1: psci: support Arm SMCCC_VERSION function ID

As per Arm SMCCC v1.1 specification [1], PSCI PSCI_FEATURES function ID
should report Arm Architecture Call SMCCC_VERSION as supported when
the secure firmware supports both PSCI PSCI_FEATURES function ID and
Arm SMCCC_VERSION function ID.

Link: [1] https://developer.arm.com/docs/den0028/latest
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic_boot: use "%#lx" to print unsigned long, not "0x%"PRIxPA

In 32-bit builds with CFG_CORE_LARGE_PHYS_ADDR=y, PRIxPA is "llx"
which is not the recommended format to print an unsigned long

core: generic_boot: use "%#lx" to print unsigned long, not "0x%"PRIxPA

In 32-bit builds with CFG_CORE_LARGE_PHYS_ADDR=y, PRIxPA is "llx"
which is not the recommended format to print an unsigned long int.
Use "lx" instead to avoid warnings with some compilers.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-ls: Enable CAAM driver for PLATFORM lx2160ardb

Enable and test CAAM driver on lx2160ardb platform for
hash, ciphers and RSA

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-

core: plat-ls: Enable CAAM driver for PLATFORM lx2160ardb

Enable and test CAAM driver on lx2160ardb platform for
hash, ciphers and RSA

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: caam: Fix alignment fault caused by caam_desc_pop()

Size of each JR Output ring entry is of 12 bytes for CAAM
using address pointer size as 64 bit. The descriptor address
pointer thus lies

drivers: caam: Fix alignment fault caused by caam_desc_pop()

Size of each JR Output ring entry is of 12 bytes for CAAM
using address pointer size as 64 bit. The descriptor address
pointer thus lies at 32 bit boundary in second output ring entry.
64 bit access of descriptor pointer at 32 bit boundary generates
alignment fault. To fix this, descriptor address pointer should
be accessed as two 32 bit operations.

regression_1004 Test User Crypt TA

E/TC:03 00 Core data-abort at address 0xfc09e74c (alignment fault)
E/TC:03 00 esr 0x96000021 ttbr0 0x20000fc0d7060 ttbr1 0x00000000 cidr 0x0
E/TC:03 00 cpu #3 cpsr 0x200001c4
E/TC:03 00 x0 00000000fc09e74c x1 0000000000000000
E/TC:03 00 x2 0000000000000050 x3 0000008000010100
E/TC:03 00 x4 0000000000000003 x5 00000000fc0e46e5
E/TC:03 00 x6 00000000fc09e74c x7 00000000fc09df78
E/TC:03 00 x8 0000000000000078 x9 00000000fc09c110
E/TC:03 00 x10 0000000041001900 x11 00000000ab12a911
E/TC:03 00 x12 0000000032e4d24d x13 00000000fc0e46e5
E/TC:03 00 x14 0000000000000000 x15 0000000000000000
E/TC:03 00 x16 00000000fc0e4b88 x17 0000000000000000
E/TC:03 00 x18 0000000000000000 x19 0000000000000000
E/TC:03 00 x20 000000000000270f x21 00000000fc07c000
E/TC:03 00 x22 00000000fc07c000 x23 0000000000000000
E/TC:03 00 x24 00000000fc09e74c x25 00000000fc0716d0
E/TC:03 00 x26 00000000fc09df78 x27 0000000000000000
E/TC:03 00 x28 0000000000000000 x29 00000000fc0e4900
E/TC:03 00 x30 00000000fc01ae8c elr 00000000fc01c124
E/TC:03 00 sp_el0 00000000fc0e4900
E/TC:03 00 TEE load address @ 0xfc000000
E/TC:03 00 Core data-abort at address 0xfc09e74c .debug_info+649036 (alignment fault)
E/TC:03 00 Call stack:
E/TC:03 00 0x00000000fc01c124 caam_desc_pop at core/drivers/crypto/caam/caam_desc.c:88
E/TC:03 00 0x00000000fc01b2ac caam_jr_enqueue at core/drivers/crypto/caam/caam_jr.c:510
E/TC:03 00 0x00000000fc02247c caam_cipher_block at core/drivers/crypto/caam/cipher/caam_cipher.c:331
E/TC:03 00 0x00000000fc022970 do_update_cipher at core/drivers/crypto/caam/cipher/caam_cipher.c:976
E/TC:03 00 0x00000000fc01a290 cipher_update at core/drivers/crypto/crypto_api/cipher/cipher.c:144
E/TC:03 00 0x00000000fc03562c tee_fs_fek_crypt at core/tee/tee_fs_key_manager.c:118
E/TC:03 00 0x00000000fc033dbc verify_root at core/tee/fs_htree.c:549
E/TC:03 00 0x00000000fc031edc ree_fs_open_primitive at core/tee/tee_ree_fs.c:416
E/TC:03 00 0x00000000fc0345d0 tee_fs_dirfile_open at core/tee/fs_dirfile.c:122
E/TC:03 00 0x00000000fc0321cc open_dirh at core/tee/tee_ree_fs.c:530
E/TC:03 00 0x00000000fc032498 ree_fs_open at core/tee/tee_ree_fs.c:604
E/TC:03 00 0x00000000fc0363dc tadb_open at core/tee/tadb.c:214
E/TC:03 00 0x00000000fc036c44 tee_tadb_ta_open at core/tee/tadb.c:633
E/TC:03 00 0x00000000fc00578c secstor_ta_open at core/arch/arm/kernel/secstor_ta.c:19
E/TC:03 00 0x00000000fc026658 system_open_ta_binary at core/pta/system.c:259
E/TC:03 00 0x00000000fc005e24 pseudo_ta_enter_invoke_cmd at core/arch/arm/kernel/pseudo_ta.c:199
E/TC:03 00 0x00000000fc0250dc tee_ta_invoke_command at core/kernel/tee_ta_manager.c:761
E/TC:03 00 0x00000000fc02b398 syscall_invoke_ta_command at core/tee/tee_svc.c:885
E/TC:03 00 0x00000000fc0123bc tee_svc_do_call at core/arch/arm/tee/arch_svc_a64.S:141
E/TC:03 00 0x00000000fc00811c thread_svc_handler at core/arch/arm/kernel/thread.c:1378
E/TC:03 00 0x00000000fc0039e0 el0_svc at core/arch/arm/kernel/thread_a64.S:639

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: caam: Add register map changes for Era 10

Era 10 changes the register map.

The updates that affect the drivers:
-new version registers are added

Signed-off-by: Ruchika Gupta <ruchika.gupt

drivers: caam: Add register map changes for Era 10

Era 10 changes the register map.

The updates that affect the drivers:
-new version registers are added

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: console: console initialization from embedded DTB

In case CFG_EMBED_DTB is enabled, get the chosen console from the
embedded DTB instead of the external DTB.

Signed-off-by: Sahil Malhotra <sa

core: console: console initialization from embedded DTB

In case CFG_EMBED_DTB is enabled, get the chosen console from the
embedded DTB instead of the external DTB.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
[ec: simplify by calling get_dt(), slightly rephrase commit log]
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (ls-lx2160ardb)

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core: boot: relax init sections from DT related resources

Move the initialization sequences that deal with device tree parsing
support out of the text_init and rodata_init sections to relax memory
p

core: boot: relax init sections from DT related resources

Move the initialization sequences that deal with device tree parsing
support out of the text_init and rodata_init sections to relax memory
pressure on them. To do so this change splits init_primary_helper()
in 2 helper functions: generic_init_primary() for resources expected
in the init sections and paged_init_primary() for resources that move
the pageable sections.

Updates inline comments to state generic_boot_init_primary() lies in
the init area, not in the unpaged area as wrongly stated prior this
change.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1)

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plat-stm32mp1: check TZC400 configuration

Core checks TZC400 configuration during initialization to ensure
DDR firewall expectations are satisfied.

Signed-off-by: Etienne Carriere <etienne.carriere

plat-stm32mp1: check TZC400 configuration

Core checks TZC400 configuration during initialization to ensure
DDR firewall expectations are satisfied.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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tzc400: simplify tzc_configure_region() arguments

Change tzc_configure_region() to used the newly defined structure
tzc_region_config.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

tzc400: simplify tzc_configure_region() arguments

Change tzc_configure_region() to used the newly defined structure
tzc_region_config.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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tzc400: new api functions to print violation on device interrupt

Define new API function tzc_fail_dump() in TZC400 driver to print
a friendly trace when a failure is reported by the TZC400.

Define

tzc400: new api functions to print violation on device interrupt

Define new API function tzc_fail_dump() in TZC400 driver to print
a friendly trace when a failure is reported by the TZC400.

Define new API function tzc_int_clear() to clear the TZC400 interrupt
status.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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tzc400: remove useless traces from tzc_dump_state()

Remove "enter"/"exit" trace messages and those related to not
implemented filters from tzc_dump_state().

Signed-off-by: Etienne Carriere <etienne

tzc400: remove useless traces from tzc_dump_state()

Remove "enter"/"exit" trace messages and those related to not
implemented filters from tzc_dump_state().

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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tzc400: add API functions to get firewall configuration

This change modified TZC400 driver to export functions for a platform
to get memory region configuration.

On platform running OP-TEE from a s

tzc400: add API functions to get firewall configuration

This change modified TZC400 driver to export functions for a platform
to get memory region configuration.

On platform running OP-TEE from a secure DRAM protected from a TZC400
device, OP-TEE Core cannot reconfigure TZC400 for the region is executes
into. The new driver API functions allows such platform at least to
check that TZC400 configuration matches the configuration Core is
statically built with.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: define platform flavors per DTS file

Identify platform flavors from targeted embedded DTS file.

Supported platform flavors are 157A_DK1, 157C_DK2, 157C_ED1 and
157C_EV1. They relate

plat-stm32mp1: define platform flavors per DTS file

Identify platform flavors from targeted embedded DTS file.

Supported platform flavors are 157A_DK1, 157C_DK2, 157C_ED1 and
157C_EV1. They relate to 2 SoC variants and 4 ST boards.

Supported SoC variants are 157A and 157C. The later implements a
cryptography computation hardware accelerator. Supported ST boards
are DK1, DK2, ED1 and EV1. The 2 first integrate a 500MByte DDR while
the 2 later integrate a 1GByte DDR.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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dts: stm32mp1: bump to Linux kernel v5.6.10 DTS files

Synchronize with STM32MP15 DTS files from Linux kernel v5.6.10.

Changes made on DTS/DTSI file from Linux kernel v5.6.10:
- stm32mp151.dtsi: add

dts: stm32mp1: bump to Linux kernel v5.6.10 DTS files

Synchronize with STM32MP15 DTS files from Linux kernel v5.6.10.

Changes made on DTS/DTSI file from Linux kernel v5.6.10:
- stm32mp151.dtsi: add ETZPC node, declare PSCI v1.0.
- stm32mp157a-dk1.dts: disable RCC secure-status.
- stm32mp157c-dk2.dts: disable RCC secure-status.
- stm32mp157c-ed1.dts (included by ev1): disable RCC secure-status.
- Remove resources related to input DT bindings using explicit inline
comments as those are under Linux kernel GPLv2 licensing model.

ETZPC node useless in non-secure Linux kernel but needed by secure
world.

RCC node remains disabled for the secure side so that RCC TZ
hardening is disabled since mainline Linux kernel and U-Boot
do not support SCMI clocks and reset domains. IWDG1, ETZPC, STGEN
and CRYP1 devices are described to ease their later integration.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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dt-bindings: update stm32-pinfunc.h

Update DT bindings for stm32 pin control with the Linux kernel v5.6.10
on which we want to synchronize DTS file with.

Signed-off-by: Etienne Carriere <etienne.ca

dt-bindings: update stm32-pinfunc.h

Update DT bindings for stm32 pin control with the Linux kernel v5.6.10
on which we want to synchronize DTS file with.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: stm32_i2c: fixup typo in sec_cfg field description

Fixup typo in i2c_cfg::sec_cfg description inline comment.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome For

drivers: stm32_i2c: fixup typo in sec_cfg field description

Fixup typo in i2c_cfg::sec_cfg description inline comment.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: stm32_i2c: refine trace messages

Mostly change trace message from error level to debug level.
Remove useless 1st space character in trace messages.
Use PRI* and # flag characters were appli

drivers: stm32_i2c: refine trace messages

Mostly change trace message from error level to debug level.
Remove useless 1st space character in trace messages.
Use PRI* and # flag characters were applicable.
Fix indentation.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: stm32_i2c: allow any bus frequency

Do not limit I2C bus to 3 frequencies (100KHz, 400KHz, 1MHz). Instead
allow for any frequency up to 1MHz. Depending on the requested frequency
defined in

drivers: stm32_i2c: allow any bus frequency

Do not limit I2C bus to 3 frequencies (100KHz, 400KHz, 1MHz). Instead
allow for any frequency up to 1MHz. Depending on the requested frequency
defined in clock-frequency DT entry, use the I2C spec data from either
Standard, Fast or Fast Plus mode.

This change removes use of rate IDs and use instead the rate value
itself as identifiers, allowing more flexible implementation.

Changes local variable clock_src in i2c_setup_timing() from uint32_t
to unsigned long for consistency.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: stm32_i2c: don't recompute I2C timings setting

Save I2C timing configuration when computed and reused it when
needing the same frequency later on.

Signed-off-by: Etienne Carriere <etienne.

drivers: stm32_i2c: don't recompute I2C timings setting

Save I2C timing configuration when computed and reused it when
needing the same frequency later on.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-stm32mp1: PSCI_SYSTEM_OFF support

Implement PSCI_SYSTEM_OFF command when STPMIC1 is used.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@foris

plat-stm32mp1: PSCI_SYSTEM_OFF support

Implement PSCI_SYSTEM_OFF command when STPMIC1 is used.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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