plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), c

plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), check that they are not NULL, call either
gic_init() or gic_init_base_addr().

We can move most of this logic into gic_init_base_addr(), while
platform-specific code will supply only base physical addresses for
distributor and CPU interface. This will simplify and align platform
code.

ST32MP1 had more complex logic, as it used io_pa_or_va_secure() to get
MMIO range addresses. However, as main_init_gic() called
assert(cpu_mmu_enabled()), there is no sense in using
io_pa_or_va_secure(), because we already ensured that VA will be
always used. Thus assert() call was moved to gic_init_base_addr(), and
STM32MP1 were aligned with other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_gpio: Fix register access before enabling clocks

The valid_gpio_config() function accesses the GPIO register
before the clock is enabled, which leads to the assert always
failing when

drivers: stm32_gpio: Fix register access before enabling clocks

The valid_gpio_config() function accesses the GPIO register
before the clock is enabled, which leads to the assert always
failing when using stm32_gpio_set_output_level().

Signed-off-by: Loïc Bauer <loic.bauer@socomec.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: crypto: se050: panic on initialization error

Failure to initialize the SE05x device is a critical operation as it will
effectively disable ciphers configured at build time.

This also match

drivers: crypto: se050: panic on initialization error

Failure to initialize the SE05x device is a critical operation as it will
effectively disable ciphers configured at build time.

This also matches the behaviour implemented by the other crypto drivers.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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core: ls: fix GIC offset for ls1043a rev1 and rev1.1

GIC offsets are different on ls1043a depending of the SoC revision
1 or 1.1

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by

core: ls: fix GIC offset for ls1043a rev1 and rev1.1

GIC offsets are different on ls1043a depending of the SoC revision
1 or 1.1

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: remove CAAM endianness definitions from conf.mk

Remove CAAM endianness definition (CFG_CAAM_LITTLE_ENDIAN and
CFG_CAAM_BIG_ENDIAN) from conf.mk as it is already defined in
crypto_conf.mk

core: ls: remove CAAM endianness definitions from conf.mk

Remove CAAM endianness definition (CFG_CAAM_LITTLE_ENDIAN and
CFG_CAAM_BIG_ENDIAN) from conf.mk as it is already defined in
crypto_conf.mk

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto/aspeed: ast2600: Add HACE HW hash support

Aspeed AST2600 Hash and Crypto Engine (HACE) is designated to
accelerate the throughput of hash and symmetric encryption/decryption.

This patch adds

crypto/aspeed: ast2600: Add HACE HW hash support

Aspeed AST2600 Hash and Crypto Engine (HACE) is designated to
accelerate the throughput of hash and symmetric encryption/decryption.

This patch adds the driver support for AST2600 HACE to provide
HW-assisted hash for the SHA family. The initial driver structure
for Aspeed crypto engines is also constructed.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: change return type for tee_entry_std() TEE_Result

Changes the return type for the function tee_entry_std() to TEE_Result
in order to make it independent of optee_smc.h. tee_entry_std() is also

core: change return type for tee_entry_std() TEE_Result

Changes the return type for the function tee_entry_std() to TEE_Result
in order to make it independent of optee_smc.h. tee_entry_std() is also
called from yielding_call_with_arg() and it doesn't make sense for that
function to return values based on the SMC ABI.

With this we're doing an ABI change for FF-A, but that should not make a
difference for the driver since that only test for 0 or !0. In addition
if !0 is returned the communication has broken down completely so there
not much left to recover from. Note that this patch does not require
changes in the Linux kernel driver.

Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove references to OPTEE_SMC_SHM_CACHED

Removes references to OPTEE_SMC_SHM_CACHED in architecture independent
code, the references are replaces by TEE_MATTR_CACHE_CACHED which is
more accur

core: remove references to OPTEE_SMC_SHM_CACHED

Removes references to OPTEE_SMC_SHM_CACHED in architecture independent
code, the references are replaces by TEE_MATTR_CACHE_CACHED which is
more accurate.

Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move NOTIF_VALUE_DO_BOTTOM_HALF assert to thread_optee_smc.c

Moves the compile assertion that NOTIF_VALUE_DO_BOTTOM_HALF matches
OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF in core/kernel/notif

core: move NOTIF_VALUE_DO_BOTTOM_HALF assert to thread_optee_smc.c

Moves the compile assertion that NOTIF_VALUE_DO_BOTTOM_HALF matches
OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF in core/kernel/notif.c to
core/arch/arm/kernel/thread_optee_smc.c to keep dependencies to
optee_smc.h in architecture specific code.

Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: vm.c: don't include sm/optee_smc.h

sm/optee_smc.h isn't needed in this file any longer so remove the
include statement.

Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Je

core: vm.c: don't include sm/optee_smc.h

sm/optee_smc.h isn't needed in this file any longer so remove the
include statement.

Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto: fix the RSA public key size for TA signature verification

The size of the RSA public key allocation should be based on the modulus
size in bits.

Fixes: 064663e8b ("core: crypto: add s

core: crypto: fix the RSA public key size for TA signature verification

The size of the RSA public key allocation should be based on the modulus
size in bits.

Fixes: 064663e8b ("core: crypto: add struct shdr helper functions")
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: move tee_mm.c to core/mm

Move tee_mm.c from core/arch/arm/mm to core/mm to reuse it with new
architectures.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etien

core: mm: move tee_mm.c to core/mm

Move tee_mm.c from core/arch/arm/mm to core/mm to reuse it with new
architectures.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: move boot.h to core/include/kernel

Move boot.h from core/arch/arm/include/kernel/ to core/include/kernel to
avoid duplicating it in arch folder if we build for a new architecture.

Sig

core: kernel: move boot.h to core/include/kernel

Move boot.h from core/arch/arm/include/kernel/ to core/include/kernel to
avoid duplicating it in arch folder if we build for a new architecture.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: tee_ta_manager.c: remove arm.h from includes

Header file arm.h is not used in tee_ta_manager.c, remove it from includes
such that can reuse it with new architecture.

Signed-off-by: Ma

core: kernel: tee_ta_manager.c: remove arm.h from includes

Header file arm.h is not used in tee_ta_manager.c, remove it from includes
such that can reuse it with new architecture.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split core/arch/arm/mm/core_mmu.c

Splits core/arch/arm/mm/core_mmu.c into one generic and one architecture
specific file.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene

core: split core/arch/arm/mm/core_mmu.c

Splits core/arch/arm/mm/core_mmu.c into one generic and one architecture
specific file.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_table_write_barrier()

Adds the special barrier core_mmu_table_write_barrier() which is
supposed to be used to make sure that writes to translation tables has
become visible.

Revi

core: add core_mmu_table_write_barrier()

Adds the special barrier core_mmu_table_write_barrier() which is
supposed to be used to make sure that writes to translation tables has
become visible.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce TRUSTED_{S,D}RAM_*

Introduces TRUSTED_{S,D}RAM_* intended to replace TZ{S,D}RAM_* on the
longer term. In this patch we're cleaning up core_mmu.c to make it
less architecture dependen

core: introduce TRUSTED_{S,D}RAM_*

Introduces TRUSTED_{S,D}RAM_* intended to replace TZ{S,D}RAM_* on the
longer term. In this patch we're cleaning up core_mmu.c to make it
less architecture dependent.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split core_mmu_private.h

Splits core_mmu_private.h into <mm/core_mmu_arch.h> and <mm/core_mmu.h>

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.bou

core: split core_mmu_private.h

Splits core_mmu_private.h into <mm/core_mmu_arch.h> and <mm/core_mmu.h>

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split core/arch/arm/include/mm/core_mmu.h

Splits core/arch/arm/include/mm/core_mmu.h into one generic and one
architecture specific file.

Reviewed-by: Jerome Forissier <jerome@forissier.org>

core: split core/arch/arm/include/mm/core_mmu.h

Splits core/arch/arm/include/mm/core_mmu.h into one generic and one
architecture specific file.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm{32,64}.h: add "memory" constraint

Adds the missing memory constraint to the inline assembly instructions
isb, dsb, dmb, sev, wfe and wfi.

Reviewed-by: Jerome Forissier <jerome@forissier.o

core: arm{32,64}.h: add "memory" constraint

Adds the missing memory constraint to the inline assembly instructions
isb, dsb, dmb, sev, wfe and wfi.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add support for SPMC at EL3

Adds support for SPMC at EL3 with CFG_CORE_EL3_SPMC. This is from OP-TEE
point of view almost identical to CFG_CORE_SEL2_SPMC with SPMC at S-EL2.

The previously S-

core: add support for SPMC at EL3

Adds support for SPMC at EL3 with CFG_CORE_EL3_SPMC. This is from OP-TEE
point of view almost identical to CFG_CORE_SEL2_SPMC with SPMC at S-EL2.

The previously S-EL2 specific functions mobj_ffa_sel2_spmc_new() and
mobj_ffa_sel2_spmc_delete() are renamed to mobj_ffa_spmc_new() and
mobj_ffa_spmc_delete() respectively since they are no longer reserved to
used only with SPMC at S-EL2.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: stop using FFA_MEMORY_REGION_FLAG_TIME_SLICE

FFA_MEMORY_REGION_FLAG_TIME_SLICE is an optional feature and might not
be available in the SPM. So drop this flag for better compatibility.

A

core: ffa: stop using FFA_MEMORY_REGION_FLAG_TIME_SLICE

FFA_MEMORY_REGION_FLAG_TIME_SLICE is an optional feature and might not
be available in the SPM. So drop this flag for better compatibility.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: correct response to FFA_INTERRUPT

When a secure interrupts is delivered by the SPM to OP-TEE the correct
response is FFA_MSG_WAIT, not FFA_SUCCESS_32 as was used previously. So
fix this.

core: ffa: correct response to FFA_INTERRUPT

When a secure interrupts is delivered by the SPM to OP-TEE the correct
response is FFA_MSG_WAIT, not FFA_SUCCESS_32 as was used previously. So
fix this.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: fix spmc_rxtx_map()

Adds the missing calls to virt_to_phys() when registering the rxtx
buffers with the SPMC.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklan

core: ffa: fix spmc_rxtx_map()

Adds the missing calls to virt_to_phys() when registering the rxtx
buffers with the SPMC.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: enable uart IT with TF-A and GICv3

With GICv3 TF-A doesn't need to know which interrupts are destined to
S-EL1 since this is programmed directly in the GICv3. On GICv2 that's
not poss

plat-vexpress: enable uart IT with TF-A and GICv3

With GICv3 TF-A doesn't need to know which interrupts are destined to
S-EL1 since this is programmed directly in the GICv3. On GICv2 that's
not possible so fix the ifdefs for this.

Always keep uart interrupts disabled with CFG_VIRTUALIZATION=y since
that requires more work to sort out.

Fixes: 41985789f3bd ("plat-vexpress: disable uart IT with TF-A and GICv3")
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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