core: crypto: add Ed25519 support

Put in place Ed25519 core functionality and support it for
OP-TEE crypto syscalls.

Signed-off-by: Valerii Chubar <valerii_chubar@epam.com>
Signed-off-by: Sergiy Ki

core: crypto: add Ed25519 support

Put in place Ed25519 core functionality and support it for
OP-TEE crypto syscalls.

Signed-off-by: Valerii Chubar <valerii_chubar@epam.com>
Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: libtomcrypt: add Ed25519 support

Enable Ed25519 implementation of libtomcrypt and add the OP-TEE wrappers.

Signed-off-by: Valerii Chubar <valerii_chubar@epam.com>
Signed-off-by: Sergiy Kibrik

core: libtomcrypt: add Ed25519 support

Enable Ed25519 implementation of libtomcrypt and add the OP-TEE wrappers.

Signed-off-by: Valerii Chubar <valerii_chubar@epam.com>
Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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libtomcrypt: ctr_encrypt(): adjust for OP-TEE CE accelerated routines

Commit 8411e6ad673d ("Squashed commit upgrading to
libtomcrypt-1.18.2-develop-20220913") is missing a local change in
ctr_encryp

libtomcrypt: ctr_encrypt(): adjust for OP-TEE CE accelerated routines

Commit 8411e6ad673d ("Squashed commit upgrading to
libtomcrypt-1.18.2-develop-20220913") is missing a local change in
ctr_encrypt.c which should have been carried over from the previous
import branch, see commit 5a913ee74d3c ("Squashed commit upgrading to
libtomcrypt-1.18.2-develop-20180819"). The missing code is from commit
c54b6344cc4e ("core: crypto: cleanup and fix CE accelerated AES CTR").
Most of that commit was made irrelevant after the move of accelerated
code out of core/lib/libtomcrypt/src, except for the bits that touch
ctr_encrypt() in core/lib/libtomcrypt/src/modes/ctr/ctr_encrypt.c.

Re-introduce the needed change. Fixes failures in xtest 4003 when
CFG_CRYPTO_WITH_CE=y.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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Squashed commit upgrading to libtomcrypt-1.18.2-develop-20220913

Squash merging branch import/libtomcrypt-1.18.2-develop-20220913

cedf001cc024 ("ci: rust: apply upstream patch to fix failure in au

Squashed commit upgrading to libtomcrypt-1.18.2-develop-20220913

Squash merging branch import/libtomcrypt-1.18.2-develop-20220913

cedf001cc024 ("ci: rust: apply upstream patch to fix failure in authentication-rs")
1c8f27245e4f ("core: ltc: fix .qord value in DSA sign and verify")
87431ada69ed ("libtomcrypt: define LTC_MPI at the same time as LTC_DER")
7d8cdbb85a57 ("core: ltc: add missing <string_ext.h>")
fa3ac5998cc7 ("core: ltc: import sub.mk files from master and update")
35f56bc9f8c4 ("core: libtomcrypt: Remove prng_state* NULL pointer check from x25519_make_key()")
85140c1f9be4 ("core: ltc: fix missing mutex unlock")
02f519845bbe ("core: ltc: add SM2 curve parameters")
757ab2c4462d ("core: ltc: make key in accel_ecb_encrypt() and accel_ecb_decrypt() const")
15c897fbe000 ("core: ltc: fix 'switch case misses default'")
6276df75362f ("core: ltc: add custom DH key generation function dh_make_key()")
1da50b460270 ("core: ltc: tomcrypt_custom.h: OP-TEE thread support")
6f78a99a6e8c ("libtomcrypt: implement zeromem() with memzero_explicit()")
90eaafe0f10f ("core: LTC use only _CFG_CORE_LTC_ variables")
fbd6fb746576 ("LTC: add GHASH acceleration")
e3ff5f701223 ("ltc: make cipher_descriptor a pointer to descriptors")
fbe13c05804d ("ltc: make hash_descriptor a pointer to descriptors")
6c193f5e561a ("ltc: make prng_descriptor a pointer to descriptors")
9f40d2838fa3 ("libtomcrypt: tomcrypt_private.h: add HASH_PROCESS_NBLOCKS")
4f6b32962d15 ("ECC: optimize the pool of temporary variables")
955eced29a6f ("Import LibTomCrypt v1.18.2 branch "develop" (Sep 13, 2022)")
3717d76418c8 ("Remove LibTomCrypt")

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: versal: mailbox communication

Mailbox driver to communicate with the PLM firmware executing on the
Microblaze processor.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: J

drivers: versal: mailbox communication

Mailbox driver to communicate with the PLM firmware executing on the
Microblaze processor.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-versal: define the length of the cache line

Explicitly define the length of the cache line for the Versal ACAP
platform.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerom

plat-versal: define the length of the cache line

Explicitly define the length of the cache line for the Versal ACAP
platform.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: sp: add support for SPs in the FIP

This commit introduces support for using SPs from the FIP. TF-A offers a
mechanism to encapsulate an SP image and its manifest into an SP package
and add tha

core: sp: add support for SPs in the FIP

This commit introduces support for using SPs from the FIP. TF-A offers a
mechanism to encapsulate an SP image and its manifest into an SP package
and add that to the FIP. During boot BL2 will load these packages into
memory and the SPMC manifest is used to pass the load addresses to the
SPMC. The SP package contains a header, the SP manifest and the SP image
itself [1].

For loading the SP packages the existing embedded SP handling code is
mostly reused. The only difference is that instead of a scattered array
that's created at build time the SP packages are discovered at runtime
and collected into a linked list.

Link: [1] https://trustedfirmware-a.readthedocs.io/en/v2.6/components/secure-partition-manager.html#secure-partition-packages
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: sp: fix sp_dt_get_u64() alignment issue

In the SP DT files 64-bit values are represented by two 32-bit cells.
When loaded into memory, the address of such value might not be 64-bit
aligned. Cu

core: sp: fix sp_dt_get_u64() alignment issue

In the SP DT files 64-bit values are represented by two 32-bit cells.
When loaded into memory, the address of such value might not be 64-bit
aligned. Currently sp_dt_get_u64() simply dereferences a pointer to such
value. This compiles to a 64-bit load instruction, which causes an
alignment fault if the address was not 64-bit aligned.

Replace the direct dereferencing with the fdt64_ld() helper function
which only uses byte loads.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: sp: add DT UUID helper function

Adds helper function to read a UUID from the SP manifest DT and parse it
into a TEE_UUID struct.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-

core: sp: add DT UUID helper function

Adds helper function to read a UUID from the SP manifest DT and parse it
into a TEE_UUID struct.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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drivers: stm32_i2c: optimize the master receive path

Early error detection prevents an invalid read request made to the
device from blocking the bus for the whole transfer timeout.

Signed-off-by: J

drivers: stm32_i2c: optimize the master receive path

Early error detection prevents an invalid read request made to the
device from blocking the bus for the whole transfer timeout.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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se050: glue: i2c_stm32

To add support in the device tree - since the NXP SE05x device node
has not been agreed yet - the user must provide an alias to the bus
where the device is located.

Once the

se050: glue: i2c_stm32

To add support in the device tree - since the NXP SE05x device node
has not been agreed yet - the user must provide an alias to the bus
where the device is located.

Once the SE05X node has been agreed, support will be added to all
OP-TEE supported platforms.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: stm32_i2c: fix read operations on I2C_MODE_MASTER mode

One of the valid conditions that leads to the generation of a NACK
is when the controller-receiver signals the end of the transfer
to

drivers: stm32_i2c: fix read operations on I2C_MODE_MASTER mode

One of the valid conditions that leads to the generation of a NACK
is when the controller-receiver signals the end of the transfer
to the target transmitter.

The code being fixed - not clearing the NACK - was causing subsequent
write operations to fail.

This has been validated using the NXP SE050 device.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: rpc: log error when allocation fails in non-secure world

The error messages printed when the non-secure world fails to allocate
shared memory may be misleading misleading:

E/LD: init_elf:45

core: rpc: log error when allocation fails in non-secure world

The error messages printed when the non-secure world fails to allocate
shared memory may be misleading misleading:

E/LD: init_elf:453 sys_open_ta_bin(cb3e5ba0-adf1-11e0-998b-0002a5d5c51b)
E/TC:? 0 ldelf_init_with_ldelf:131 ldelf failed with res: 0xffff000c

This looks like an out-of-memory condition (0xffff000c =
TEE_ERROR_OUT_OF_MEMORY) in the TEE core ("E/TC"), in other words
insufficient core heap space. Add the following message to help pinpoint
the issue:

E/TC:? 0 get_rpc_alloc_res:645 RPC allocation failed. Non-secure world result: ret=0xffff000c ret_origin=0x2

This situation can be reproduced by killing tee-supplicant and invoking
a TA. When the CA is interrupted (Ctrl-C), the above log is printed.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Squashed commit upgrading to zlib v1.12.2

Squash merging branch import/zlib-1.12.2

67d1c836b46d ("core: zlib: fix build warning when _LFS64_LARGEFILE is not defined")
82826342c694 ("zlib: add SPD

Squashed commit upgrading to zlib v1.12.2

Squash merging branch import/zlib-1.12.2

67d1c836b46d ("core: zlib: fix build warning when _LFS64_LARGEFILE is not defined")
82826342c694 ("zlib: add SPDX license identifiers")
bbdade0f5924 ("zlib: set zconf.h options for embedded TS")
449dd56422ca ("Import zlib v1.12.2")

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add missing pauth key saving in foreign interrupt handler

When a foreign interrupt (non-secure) is trapped in OP-TEE the state of
the current thread is saved similarly to when an RPC is perfor

core: add missing pauth key saving in foreign interrupt handler

When a foreign interrupt (non-secure) is trapped in OP-TEE the state of
the current thread is saved similarly to when an RPC is performed.

With pointer authentication enabled two more registers which are part of
the current context, APIAKEYHI-EL1 and APIAKEYLO-EL1, are added. These
registers contains a key needed for pointer authentication. This key is
unique per context so it must always be saved and restored when
switching context.

Prior to this patch the step where this key is saved in the foreign
interrupt handler was missing, so fix this by adding the missing step.

Fixes: 2b06f9dede33 ("Add basic pointer authentication support for TA's")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-versal: mmap regions

Increase the number of regions in preparation for the merge of
additional drivers.

The value has been chosen using the other more stable platforms
as a reference.

Signed-

plat-versal: mmap regions

Increase the number of regions in preparation for the merge of
additional drivers.

The value has been chosen using the other more stable platforms
as a reference.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-versal: build tee-raw.bin image

This commit generates the tee-raw.bin image so the user can
pass the boot address on the bif file.

The bif file could look like this

the_ROM_image:
{
image {

plat-versal: build tee-raw.bin image

This commit generates the tee-raw.bin image so the user can
pass the boot address on the bif file.

The bif file could look like this

the_ROM_image:
{
image {
{ type=bootimage, file=vpl.pdi }
{ type=bootloader, file=plm.elf }
{ core=psm, file=psmfw.elf }
}

image {
id = 0x1c000000, name=apu_subsystem
{ type=raw, load=0x00001000, file=versal.dtb }
{ core=a72-0, exception_level=el-3, trustzone, file=bl31.elf }
{ core=a72-0, exception_level=el-2, file=u-boot.elf }
{ core=a72-0, exception_level=el-1, trustzone, load=0x60000000,
startup=0x60000000, file=tee-raw.bin }
}
}

For additional information on how to build this platform, please refer
to https://github.com/OP-TEE/build/versal.mk

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: drivers: nxp: Add LX2160A-series SecMon driver

- This driver implements reading the entire NXP LX2160-series Security
Monitor (SecMon) module.
- To enable the SecMon driver, the optee-os bui

core: drivers: nxp: Add LX2160A-series SecMon driver

- This driver implements reading the entire NXP LX2160-series Security
Monitor (SecMon) module.
- To enable the SecMon driver, the optee-os build requires the
CFG_LS_SEC_MON flag.

Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: reset platform with reset controller device

Change platform stm32mp1 PSCI_SYSTEM_RESET implementation to rely
on reset controller framework to proceed a full platform reset insead
of

plat-stm32mp1: reset platform with reset controller device

Change platform stm32mp1 PSCI_SYSTEM_RESET implementation to rely
on reset controller framework to proceed a full platform reset insead
of a platform specific sequence. This change makes MP13 variants to
now support PSCI system reset feature.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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dt-bindings: define system reset controller for stm32mp1 flavors

Define DT binding ID related to system reset controller, for both
STM32MP15 and STM32MP13 variants.

Acked-by: Jens Wiklander <jens.w

dt-bindings: define system reset controller for stm32mp1 flavors

Define DT binding ID related to system reset controller, for both
STM32MP15 and STM32MP13 variants.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: scmi-msg: Propagate errors from platform voltd_get_level

plat_scmi_voltd_get_level is refactored to return an SCMI error code and
retrieve the voltage via an out parameter. This allows erro

drivers: scmi-msg: Propagate errors from platform voltd_get_level

plat_scmi_voltd_get_level is refactored to return an SCMI error code and
retrieve the voltage via an out parameter. This allows errors from the
platform SCMI server implementation to be propagated to the REE.

The implementation for stm32mp1 is updated to handle at least some
possible errors.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Anton Eliasson <anton.eliasson@axis.com>

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plat-stm32mp1: add Avenger96 board with STM32MP157A based DHCOR SoM

The dts(i) files are imported from Linux 5.19-rc6.

Changes made to the imported dts(i) files:
- Enable rcc as on other boards
- A

plat-stm32mp1: add Avenger96 board with STM32MP157A based DHCOR SoM

The dts(i) files are imported from Linux 5.19-rc6.

Changes made to the imported dts(i) files:
- Enable rcc as on other boards
- Allow iwdg2 for usage in non-secure world

Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: add STM32MP157C based DHCOM SoM on PDK2 baseboard

The dts(i) files are imported from Linux 5.19-rc6.

Changes made to the imported dts(i) files:
- Drop GPLv2 licensed resources and/or

plat-stm32mp1: add STM32MP157C based DHCOM SoM on PDK2 baseboard

The dts(i) files are imported from Linux 5.19-rc6.

Changes made to the imported dts(i) files:
- Drop GPLv2 licensed resources and/or use their explicit values
- Drop cryp1 okay status as on other boards
- Drop unsupported special rcc clocks definition using comments
- Enable rcc as on other boards
- Allow iwdg2 for usage in non-secure world

Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: versal: general purpose i/o

Provide access to the GPIO controller on Versal ACAP.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.or

drivers: versal: general purpose i/o

Provide access to the GPIO controller on Versal ACAP.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: driver: rework the SC API to make compatible with the new MU driver

Rework the SC API to leverage the common MU driver.
This re-work implies the deletion of duplicate functions that are now
im

core: driver: rework the SC API to make compatible with the new MU driver

Rework the SC API to leverage the common MU driver.
This re-work implies the deletion of duplicate functions that are now
implemented in the MU driver instead

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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