core, ldelf: link: add --no-warn-execstack

When building for arm32 with GNU binutils 2.39, the linker outputs
warnings when generating some TEE core binaries (all_obj.o, init.o,
unpaged.o and tee.el

core, ldelf: link: add --no-warn-execstack

When building for arm32 with GNU binutils 2.39, the linker outputs
warnings when generating some TEE core binaries (all_obj.o, init.o,
unpaged.o and tee.elf) as well as ldelf.elf:

arm-poky-linux-gnueabi-ld.bfd: warning: atomic_a32.o: missing .note.GNU-stack section implies executable stack
arm-poky-linux-gnueabi-ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker

The permissions used when mapping the TEE core stacks do not depend on
any metadata found in the ELF file. Similarly when the TEE core loads
ldelf it already creates a non-executable stack regardless of ELF
information. Therefore we can safely ignore the warnings. This is done
by adding the '--no-warn-execstack' option.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: stack check: fix debug message

The lower limit for thread stacks printed by print_stack_limits()
when CFG_CORE_DEBUG_CHECK_STACKS=y is incorrect. It needs to be
increased by STACK_CHECK_EXTRA

core: stack check: fix debug message

The lower limit for thread stacks printed by print_stack_limits()
when CFG_CORE_DEBUG_CHECK_STACKS=y is incorrect. It needs to be
increased by STACK_CHECK_EXTRA to be consistent with the value
returned by get_stack_soft_limits(). While we're at it, improve
the SP out of range message to make it EMSG() rather than DMSG() and
show the stack limits. This makes it easier to identify in which
stack the pointer was supposed to be.

Here is an example of a stack overflow panic in thread 0:

D/TC:? 0 ldelf_syscall_open_bin:142 Lookup user TA ELF cb3e5ba0-adf1-11e0-998b-0002a5d5c51b (Secure Storage TA)
E/TC:? 0 Stack pointer out of range! 0x7e7bd618 not in [0x7e7bd630 .. 0x7e7bf030]
D/TC:? 0 print_stack_limits:179 tmp [0] 0x7e7c1c90..0x7e7c24b0
D/TC:? 0 print_stack_limits:179 tmp [1] 0x7e7c2ad0..0x7e7c32f0
D/TC:? 0 print_stack_limits:179 tmp [2] 0x7e7c3910..0x7e7c4130
D/TC:? 0 print_stack_limits:179 tmp [3] 0x7e7c4750..0x7e7c4f70
D/TC:? 0 print_stack_limits:184 abt [0] 0x7e7b8710..0x7e7b9330
D/TC:? 0 print_stack_limits:184 abt [1] 0x7e7b9950..0x7e7ba570
D/TC:? 0 print_stack_limits:184 abt [2] 0x7e7bab90..0x7e7bb7b0
D/TC:? 0 print_stack_limits:184 abt [3] 0x7e7bbdd0..0x7e7bc9f0
D/TC:? 0 print_stack_limits:189 thr [0] 0x7e7bd630..0x7e7bf030
D/TC:? 0 print_stack_limits:189 thr [1] 0x7e7bfc70..0x7e7c1670
E/TC:1 0 Panic at core/kernel/thread.c:207 <check_stack_limits>
E/TC:1 0 TEE load address @ 0x7e6e5000
E/TC:1 0 Call stack:
E/TC:1 0 0x7e6f1b10 print_kernel_stack at optee_os/core/arch/arm/kernel/unwind_arm64.c:80
E/TC:1 0 0x7e7071b8 __do_panic at optee_os/core/kernel/panic.c:24
E/TC:1 0 0x7e70cd14 check_stack_limits at optee_os/core/kernel/thread.c:207
E/TC:1 0 0x7e70dcd8 __cyg_profile_func_enter at optee_os/core/kernel/thread.c:237
E/TC:1 0 0x7e766b74 memset at optee_os/lib/libutils/isoc/newlib/memset.c:76
E/TC:1 0 0x7e768928 memzero_explicit at optee_os/lib/libutils/ext/memzero_explicit.c:22
E/TC:1 0 0x7e74de54 zeromem at optee_os/core/lib/libtomcrypt/src/misc/zeromem.c:26 (discriminator 2)
E/TC:1 0 0x7e74ddd8 burn_stack at optee_os/core/lib/libtomcrypt/src/misc/burn_stack.c:24
E/TC:1 0 0x7e74a32c rijndael_ecb_encrypt at optee_os/core/lib/libtomcrypt/src/ciphers/aes/aes.c:454
E/TC:1 0 0x7e743e44 crypto_aes_enc_block at optee_os/core/lib/libtomcrypt/aes.c:45 (discriminator 2)
E/TC:1 0 0x7e6fa1d0 decrypt_block at optee_os/core/crypto/aes-gcm-sw.c:98
E/TC:1 0 0x7e6fa2ec decrypt_pl at optee_os/core/crypto/aes-gcm-sw.c:118 (discriminator 3)
E/TC:1 0 0x7e6fa400 internal_aes_gcm_update_payload_blocks at optee_os/core/crypto/aes-gcm-sw.c:143
E/TC:1 0 0x7e6f93f4 __gcm_update_payload at optee_os/core/crypto/aes-gcm.c:246
E/TC:1 0 0x7e6f9504 operation_final at optee_os/core/crypto/aes-gcm.c:273
E/TC:1 0 0x7e6f9780 __gcm_dec_final at optee_os/core/crypto/aes-gcm.c:328
E/TC:1 0 0x7e6f9840 internal_aes_gcm_dec_final at optee_os/core/crypto/aes-gcm.c:342
E/TC:1 0 0x7e6f9a64 aes_gcm_dec_final at optee_os/core/crypto/aes-gcm.c:500
E/TC:1 0 0x7e6f85cc crypto_authenc_dec_final at optee_os/core/crypto/crypto.c:427
E/TC:1 0 0x7e7352d8 authenc_decrypt_final at optee_os/core/tee/fs_htree.c:511
E/TC:1 0 0x7e736094 tee_fs_htree_read_block at optee_os/core/tee/fs_htree.c:899
E/TC:1 0 0x7e732234 ree_fs_read_primitive at optee_os/core/tee/tee_ree_fs.c:340
E/TC:1 0 0x7e7334e8 read_dent at optee_os/core/tee/fs_dirfile.c:103
E/TC:1 0 0x7e734024 tee_fs_dirfile_open at optee_os/core/tee/fs_dirfile.c:143
E/TC:1 0 0x7e731ab4 open_dirh at optee_os/core/tee/tee_ree_fs.c:552
E/TC:1 0 0x7e731b50 get_dirh at optee_os/core/tee/tee_ree_fs.c:573
E/TC:1 0 0x7e732e38 ree_fs_open at optee_os/core/tee/tee_ree_fs.c:626
E/TC:1 0 0x7e72ec60 tadb_open at optee_os/core/tee/tadb.c:227
E/TC:1 0 0x7e72f3a0 tee_tadb_open at optee_os/core/tee/tadb.c:246 (discriminator 1)
E/TC:1 0 0x7e72ff7c tee_tadb_ta_open at optee_os/core/tee/tadb.c:643
E/TC:1 0 0x7e70fed8 secstor_ta_open at optee_os/core/kernel/secstor_ta.c:19
E/TC:1 0 0x7e706648 ldelf_syscall_open_bin at optee_os/core/kernel/ldelf_syscalls.c:145
E/TC:1 0 0x7e6f54c0 tee_svc_do_call at optee_os/core/arch/arm/tee/arch_svc_a64.S:140
E/TC:1 0 0x7e6ec780 thread_svc_handler at optee_os/core/arch/arm/kernel/thread.c:1104 (discriminator 4)
E/TC:1 0 0x7e6ea35c el0_svc at optee_os/core/arch/arm/kernel/thread_a64.S:825

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: fix handling of CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA

CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA should be included in
STACK_THREAD_SIZE and STACK_TMP_SIZE, respectively, because

core: fix handling of CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA

CFG_STACK_THREAD_EXTRA and CFG_STACK_TMP_EXTRA should be included in
STACK_THREAD_SIZE and STACK_TMP_SIZE, respectively, because not doing so
creates inconsistencies where some places use e.g., (STACK_THREAD_SIZE +
CFG_STACK_THREAD_EXTRA) while others use STACK_THREAD_SIZE only. Note
for example the discrepancy between the stack declaration:

DECLARE_STACK(stack_thread, CFG_NUM_THREADS,
STACK_THREAD_SIZE + CFG_STACK_THREAD_EXTRA, static);

...and the thread_stack_start() function:

vaddr_t thread_stack_start(void)
{
/* ... */

return thr->stack_va_end - STACK_THREAD_SIZE;
}

With this change, the _EXTRA values should also be properly taken into
account when pager is enabled, which was not the case before.

Fixes: cca7b5ebeb9b ("core: configuration switches to tune stack sizes")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge@foundries.io> (STM32MP1, SE050, pager)

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imx: dcp: switch to new alloc_cache_aligned()

Use commonized outer cache line aligned memory allocator instead of having
local implementation.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@va

imx: dcp: switch to new alloc_cache_aligned()

Use commonized outer cache line aligned memory allocator instead of having
local implementation.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add allocator for cache aligned memory

Provides new common maximum cache line aligned allocator for allocating
memory to be used when communicating with different peripherals within the
CPU.

core: add allocator for cache aligned memory

Provides new common maximum cache line aligned allocator for allocating
memory to be used when communicating with different peripherals within the
CPU.

Allocated memory can be readily used with cache maintenance operations.

This is based on core/drivers/imx/dcp/dcp_utils.c.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: sort includes in tee_misc.c

Sort includes to keep it clean.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

arm: cache_helpers.h: Add cache_get_max_line_size()

Add helper for querying outer cache line size in bytes.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklan

arm: cache_helpers.h: Add cache_get_max_line_size()

Add helper for querying outer cache line size in bytes.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm.mk: Added CFG_MAX_CACHE_LINE_SHIFT for maximum cache line size

When sharing memory between CPU and peripherals it is important that data
is accurate for all parties.

Today's CPU's has multiple

arm.mk: Added CFG_MAX_CACHE_LINE_SHIFT for maximum cache line size

When sharing memory between CPU and peripherals it is important that data
is accurate for all parties.

Today's CPU's has multiple levels for caches and their sizes are platform
specific. As there is no auto detectable way to determine cache line size
during runtime so it must be defined during compilation time.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: Add high DDR memory region

K3 devices support more than 2GB of DRAM, the extra is placed at a highmem
address of 0x880000000. If memory from this area is passed to OP-TEE
one will get the f

plat-k3: Add high DDR memory region

K3 devices support more than 2GB of DRAM, the extra is placed at a highmem
address of 0x880000000. If memory from this area is passed to OP-TEE
one will get the following error:

E/TC:1 0 std_entry_with_parg:235 Bad arg address 0x881585000

Add the highmem area to fix this.

Fixes: dfd994436ac3 ("plat-k3: Add DDR setup in k3 platform")
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-k3: Enable ARMv8 Crypto Extensions support by default

All of the currently supported K3 platforms support ARM CE, enable this
by default so it does not have to be enabled in the build command.

plat-k3: Enable ARMv8 Crypto Extensions support by default

All of the currently supported K3 platforms support ARM CE, enable this
by default so it does not have to be enabled in the build command.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-k3: drivers: Reverse RNG disabling logic

We want to be able to disable SA2UL from the command line and only be
able to enable it for supported platforms. Right now we force it on
for supported

plat-k3: drivers: Reverse RNG disabling logic

We want to be able to disable SA2UL from the command line and only be
able to enable it for supported platforms. Right now we force it on
for supported platforms and allow it to be enabled still on unsupported
ones. Reverse this.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-k3: drivers: ti-sci: Do not print error when message not acknowledged

When the system controller firmware denies a request, we are informed
of this by the lack of an acknowledge flag in the res

plat-k3: drivers: ti-sci: Do not print error when message not acknowledged

When the system controller firmware denies a request, we are informed
of this by the lack of an acknowledge flag in the response. This is
not always an error in cases when we are only testing for permissions.
Do not print error messages in this path. The TI-SCI API caller will
still print the appropriate message if needed.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

plat-k3: drivers: Set SA2UL firewall region addresses

This firewall region is normally already set to cover our RNG, but that
is not guaranteed. To ensure we actually protect the RNG with this regio

plat-k3: drivers: Set SA2UL firewall region addresses

This firewall region is normally already set to cover our RNG, but that
is not guaranteed. To ensure we actually protect the RNG with this region,
explicitly set the address here to the RNG start and end addresses.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: add CFG_REE_FS_INTEGRITY_RPMB for roll-back protection of REE

If we enable CFG_RPMB_FS and CFG_REE_FS at the same time in optee-os,
with tee-supplicant only supports REE, calls from xtest to

core: add CFG_REE_FS_INTEGRITY_RPMB for roll-back protection of REE

If we enable CFG_RPMB_FS and CFG_REE_FS at the same time in optee-os,
with tee-supplicant only supports REE, calls from xtest to
ree_fs_open() will attempt to access RPMB for roll-back protection,
which will fail because tee-supplicant can't access RPMB.

In some platforms, we only want optee-os to support
RPMB key provision checking by invoking any RPMB read/writes, but
don't care about whether contents could be read/written.
The tee-supplicant in these platform is limited to REE only, because
there's an existing issue in Linux OS causing kernel drivers failed to
support RPMB. So we need an option to prevent applications like xtest
to access RPMB when calling ree_fs_open(), but keep the ability to
call RPMB fs related apis. When we check the key thru RPMB read.
If key is provisioned, tee-supplicant will return
TEEC_ERROR_ITEM_NOT_FOUND. If not, optee-os will return
TEE_ERROR_STORAGE_NOT_AVAILABLE.

How-tested: execute `xtest -t regression` with optee-os CFG_REE_FS=y
and CFG_RPMB_FS=y. optee-client RPMB_EMU=n
Many testcases will fail. (ex: case 1004)

Signed-off-by: Judy Wang <wangjudy@microsoft.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: enable the CAAM driver on mx7ulpevk

Enable the CAAM for mx7ulpevk.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: crypto_conf: set CAAM configuration for mx7ulpevk

Set CAAM configuration for the mx7ulp platform.
On mx7ulp, JRs share the same interrupt line. To avoid conflict with the
non-secure world

core: imx: crypto_conf: set CAAM configuration for mx7ulpevk

Set CAAM configuration for the mx7ulp platform.
On mx7ulp, JRs share the same interrupt line. To avoid conflict with the
non-secure world, disable the use of JR interrupt in OPTEE.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: add support imx93evk platform

Add the support for imx93evk platform.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-b

core: imx: add support imx93evk platform

Add the support for imx93evk platform.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add imx93 SoC ID

Add the imx93 SoC ID.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklan

core: imx: add imx93 SoC ID

Add the imx93 SoC ID.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add imx93 registers

Add the imx93 registers.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.

core: imx: add imx93 registers

Add the imx93 registers.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: simplify the error macro message

Simplify the error macro message for less maintenance when it comes to
introduce new platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Revi

core: imx: simplify the error macro message

Simplify the error macro message for less maintenance when it comes to
introduce new platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: se050: optional I2C access via trampoline

Platforms with secure I2C buses (i.e: STM32MP1) or those with only
a secure element on the bus might prefer not to delegate the I2C
traffic to the

drivers: se050: optional I2C access via trampoline

Platforms with secure I2C buses (i.e: STM32MP1) or those with only
a secure element on the bus might prefer not to delegate the I2C
traffic to the REE.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-corstone1000: add corstone1000 platform

These changes are to add corstone1000 platform to optee
core.
arch/arm/plat-vexpress is taken as a reference to make
these changes.

Signed-off-by: Vishn

plat-corstone1000: add corstone1000 platform

These changes are to add corstone1000 platform to optee
core.
arch/arm/plat-vexpress is taken as a reference to make
these changes.

Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: link: add --no-warn-rwx-segments

binutils ld.bfd generates one RWX LOAD segment by merging several sections
with mixed R/W/X attributes (.text, .rodata, .data). After version 2.38 it
also warn

core: link: add --no-warn-rwx-segments

binutils ld.bfd generates one RWX LOAD segment by merging several sections
with mixed R/W/X attributes (.text, .rodata, .data). After version 2.38 it
also warns by default when that happens [1], which breaks the build due to
--fatal-warnings. The RWX segment is not a problem for the TEE core, since
that information is not used to set memory permissions. Therefore, silence
the warning.

Link: [1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107
Link: https://sourceware.org/bugzilla/show_bug.cgi?id=29448
Reported-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: imx_i2c: update the daisy chain setting for I2C1

Looking at IMX6ULLRM Rev. 1, 11/2017 paragraph 32.6.329
says the daisy chain for SDA on I2C1 on imx6ull-evk is 2 not 1.

Signed-off-by: Tim

drivers: imx_i2c: update the daisy chain setting for I2C1

Looking at IMX6ULLRM Rev. 1, 11/2017 paragraph 32.6.329
says the daisy chain for SDA on I2C1 on imx6ull-evk is 2 not 1.

Signed-off-by: Tim Anderson <tim.anderson@foundries.io>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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core: tee_svc.c: add missing comma

Add missing comma to fix the following error:

$ make -s PLATFORM=vexpress-qemu_armv8a CFG_TA_PAUTH=y CFG_MEMTAG=y
core/tee/tee_svc.c:371:9: error: expected ‘}’

core: tee_svc.c: add missing comma

Add missing comma to fix the following error:

$ make -s PLATFORM=vexpress-qemu_armv8a CFG_TA_PAUTH=y CFG_MEMTAG=y
core/tee/tee_svc.c:371:9: error: expected ‘}’ before ‘{’ token
371 | {
| ^
core/tee/tee_svc.c:280:44: note: to match this ‘{’
280 | const struct tee_props tee_propset_tee[] = {
| ^

Fixes: a0e8ffe9ba8f ("core: add support for MTE")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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