History log of /optee_os/core/ (Results 2051 – 2075 of 6456)
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9e7f74ce19-Oct-2021 Clement Faure <clement.faure@nxp.com>

pta: imx: add OCOTP PTA

Add a OCOTP PTA for i.MX platforms. This PTA exposes two commands:
- the read of OCOTP shadow registers.
- the read of the platform UID.

Signed-off-by: Clement Faure <clem

pta: imx: add OCOTP PTA

Add a OCOTP PTA for i.MX platforms. This PTA exposes two commands:
- the read of OCOTP shadow registers.
- the read of the platform UID.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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e91fa6a019-Oct-2021 Clement Faure <clement.faure@nxp.com>

pta: imx: add DIGPROG PTA

Add an i.MX PTA to get the platform digprog value.
This 32 bits value holds the SOC type and the minor and major revision
number.

Signed-off-by: Clement Faure <clement.fau

pta: imx: add DIGPROG PTA

Add an i.MX PTA to get the platform digprog value.
This 32 bits value holds the SOC type and the minor and major revision
number.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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fc82e62219-Dec-2022 Jens Wiklander <jens.wiklander@linaro.org>

core: finalize scall layer

Finalizes the new scall layer by renaming remaining files so the generic
scall layer resides in core/include/kernel/scall.h and
core/kernel/scall.c.

New architectures are

core: finalize scall layer

Finalizes the new scall layer by renaming remaining files so the generic
scall layer resides in core/include/kernel/scall.h and
core/kernel/scall.c.

New architectures are expected to provide a
core/arch/arm/include/kernel/arch_scall.h with functions needed to deal
with the architecture specific struct thread_scall_regs usage in
core/kernel/scall.c.

New architectures are also expected to provide an implementation of
scall_save_panic_stack() called from scall_sys_return_helper().

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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a0ea786e19-Dec-2022 Jens Wiklander <jens.wiklander@linaro.org>

core: provide scall_save_panic_stack()

Provides an architecture specific function scall_save_panic_stack() in
core/arch/arm/kernel/arch_scall.c. This function and its helpers are
extracted from core

core: provide scall_save_panic_stack()

Provides an architecture specific function scall_save_panic_stack() in
core/arch/arm/kernel/arch_scall.c. This function and its helpers are
extracted from core/arch/arm/tee/arch_svc.c.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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99d119b019-Dec-2022 Jens Wiklander <jens.wiklander@linaro.org>

core: provide arch_scall.h

Provide scall functions to deal with the layout of the architecture
specific struct thread_scall_regs. The new static inline scall_
functions are based on the old internal

core: provide arch_scall.h

Provide scall functions to deal with the layout of the architecture
specific struct thread_scall_regs. The new static inline scall_
functions are based on the old internal static functions in
core/arch/arm/tee/arch_svc.c.

This patch doesn't change any behaviour.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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ab5363c619-Dec-2022 Jens Wiklander <jens.wiklander@linaro.org>

core: introduce scall layer from svc parts

Introduces a scall layer by renaming various thread_svc* names and
_*handle_svc() functions and function pointers as a first step in doing
architecture neu

core: introduce scall layer from svc parts

Introduces a scall layer by renaming various thread_svc* names and
_*handle_svc() functions and function pointers as a first step in doing
architecture neutral syscall processing.

The name scall is used instead of syscall since the syscall_ prefix is
reserved for the functions implementing the actual syscall. While scall
is the infrastructure used to reach the syscall functions.

No files are renamed and removed at this stage. This patch doesn't
change any behaviour.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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93e54a6320-Dec-2022 Marouene Boubakri <marouene.boubakri@nxp.com>

riscv: kernel: entry.S: provide entry script

Provide core's single entry point for RV32/RV64 in S/M Modes.
For now it performs: booting primary and secondary harts. Setting stack
pointer, thread poi

riscv: kernel: entry.S: provide entry script

Provide core's single entry point for RV32/RV64 in S/M Modes.
For now it performs: booting primary and secondary harts. Setting stack
pointer, thread pointer (to thread_core_local), supervisor address
translation and protection register, clearing BSS...etc and calls to
appropriate functions to initialize the MMU and continue to boot flow
from boot.c.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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3c47d08720-Dec-2022 Marouene Boubakri <marouene.boubakri@nxp.com>

riscv: kernel: implement boot flow in boot.c

Provide an implementation of init_tee_runtime(), plat_primary_init_early()
boot_init_primary_early(), boot_init_primary_late(), boot_init_secondary()
and

riscv: kernel: implement boot flow in boot.c

Provide an implementation of init_tee_runtime(), plat_primary_init_early()
boot_init_primary_early(), boot_init_primary_late(), boot_init_secondary()
and helper functions. For now init_sec_mon() is kept to be replaced later
by a routine to initialize SBI implementation (to for example, probe for
available SBI extensions).

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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8f29a74f12-Dec-2022 Gatien Chevallier <gatien.chevallier@foss.st.com>

plat-stm32mp1: enable debug feature on non secure-closed chip

Adds a new service that enables all debug features (HPD, invasive,
non invasive debug) when the chip is not in secure-closed state.
This

plat-stm32mp1: enable debug feature on non secure-closed chip

Adds a new service that enables all debug features (HPD, invasive,
non invasive debug) when the chip is not in secure-closed state.
This feature is enabled when CFG_STM32_DEBUG_ACCESS is set to 'y'. It
defaults to CFG_TEE_CORE_DEBUG value.

By default, chip is secure open in order to make development and
allow debug purpose.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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fd9d398602-Jan-2023 Manorit Chawdhry <m-chawdhry@ti.com>

plat-k3: Increase size of high DDR memory region

With the addition of j784s4 in K3 devices, DRAM size is increased to
32GB.

Update the size of higher memory addresses to handle this.

Signed-off-by

plat-k3: Increase size of high DDR memory region

With the addition of j784s4 in K3 devices, DRAM size is increased to
32GB.

Update the size of higher memory addresses to handle this.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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17d6dc5103-Jan-2023 Jorge Ramirez-Ortiz <jorge@foundries.io>

plat-versal: program the FPGA during OP-TEE initialization

Users can program the FPGA image by placing it at
CFG_VERSAL_FPGA_DDR_ADDR.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-

plat-versal: program the FPGA during OP-TEE initialization

Users can program the FPGA image by placing it at
CFG_VERSAL_FPGA_DDR_ADDR.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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a51510ce03-Jan-2023 Jorge Ramirez-Ortiz <jorge@foundries.io>

plat-versal: allow RPMB init only on secured boards

Allow writing the RPMB key only on secured boards.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.for

plat-versal: allow RPMB init only on secured boards

Allow writing the RPMB key only on secured boards.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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09fe420b03-Jan-2023 Jorge Ramirez-Ortiz <jorge@foundries.io>

plat-versal: print platform information

Output platform information banner to the console. This includes SoC
version and the state of the hardware root of trust configuration.

Signed-off-by: Jorge

plat-versal: print platform information

Output platform information banner to the console. This includes SoC
version and the state of the hardware root of trust configuration.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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cd0d1dd603-Jan-2023 Jorge Ramirez-Ortiz <jorge@foundries.io>

drivers: versal: hardware unique key

The hardware unique key is calculated as the AS-GCM encrypted value
of the SoC DNA unique identifier.

The key source used for encryption is selectable at build

drivers: versal: hardware unique key

The hardware unique key is calculated as the AS-GCM encrypted value
of the SoC DNA unique identifier.

The key source used for encryption is selectable at build time using
the CFG_VERSAL_HUK_KEY configuration flag.

The following sources are supported
VERSAL_AES_EFUSE_USER_KEY_0 (CFG_VERSAL_HUK_KEY = 6)
VERSAL_AES_EFUSE_USER_KEY_1 (CFG_VERSAL_HUK_KEY = 7)
VERSAL_AES_PUF_KEY (CFG_VERSAL_HUK_KEY = 11)
VERSAL_AES_USER_KEY_0 (CFG_VERSAL_HUK_KEY = 12 (default))

The default configuration does not generate a secret HUK since the
key is hardcoded in the driver - it however validates the algorithm;
but security-wise it is not different than not enabling CFG_VERSAL_HUK
and therefore using the OP-TEE provided HUK stub.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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2f99ad2818-Jan-2023 Etienne Carriere <etienne.carriere@linaro.org>

core: clk: fix dt helper function description when clock is optional

Fixes clk_dt_get_by_index() and clk_dt_get_by_name() inline description
comments to state these functions return TEE_ERROR_ITEM_N

core: clk: fix dt helper function description when clock is optional

Fixes clk_dt_get_by_index() and clk_dt_get_by_name() inline description
comments to state these functions return TEE_ERROR_ITEM_NOT_FOUND when
the consumer DT node does not define a clock resource as for devices
where some clocks are optional. These functions return such error code
since commit [1].

Link: [1] 0adca93a5c68 ("core: dt_driver: differentiate error codes if property is not found")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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b609598910-Jan-2023 Etienne Carriere <etienne.carriere@linaro.org>

core: dt_driver: fix inline comment regarding clock references

Fixes inline description comments for get_of_device_func typedef and
functions dt_driver_device_from_node_idx_prop() and
fdt_get_dt_dri

core: dt_driver: fix inline comment regarding clock references

Fixes inline description comments for get_of_device_func typedef and
functions dt_driver_device_from_node_idx_prop() and
fdt_get_dt_driver_cells() as they do not only relate to clock drivers.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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c36f205e17-Jan-2023 Jorge Ramirez-Ortiz <jorge@foundries.io>

crypto: se050: update policies

Certain devices (depending on the applet) will use the common
policies for the object's read/write permissions.

This commit makes sure both are supported.

Signed-off

crypto: se050: update policies

Certain devices (depending on the applet) will use the common
policies for the object's read/write permissions.

This commit makes sure both are supported.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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9439728527-Jan-2022 Etienne Carriere <etienne.carriere@linaro.org>

core: notif: allow GIC_PPI usage for async notif

Allows to use GIC_PPI interrupts for asynchronous notification.

This change replace macro COMPILE_TIME_ASSERT() with static_assert()
as the former i

core: notif: allow GIC_PPI usage for async notif

Allows to use GIC_PPI interrupts for asynchronous notification.

This change replace macro COMPILE_TIME_ASSERT() with static_assert()
as the former is deprecated.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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63a7574813-Jan-2023 Imre Kis <imre.kis@arm.com>

core: sp: Allow v2 FIP package format

Commit [1] in Trusted Firmware-A slightly changes the SP package format
in the FIP image. The new format is compatible with the previous version
but the partiti

core: sp: Allow v2 FIP package format

Commit [1] in Trusted Firmware-A slightly changes the SP package format
in the FIP image. The new format is compatible with the previous version
but the partition manifest and the SP binary are now stored at a 4k
aligned offset in the SP package. The main reasoning behind this is to
simplify the SP load process in other SPMC implementations (i.e.
Hafnium). OP-TEE already supports loading the manifest and the SP binary
from an arbitrary offset thus it is only necessary to allow the new
package version number on FIP SP load.

Link: [1] https://github.com/ARM-software/arm-trusted-firmware/commit/2e82874cc9b7922e000dd4d7718e3153e347b1d7
Signed-off-by: Imre Kis <imre.kis@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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8501563108-Sep-2021 Fabien Parent <fparent@baylibre.com>

plat-mediatek: add support for MT8195 SoC

Add OP-TEE support for the MT8195 SoC.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed

plat-mediatek: add support for MT8195 SoC

Add OP-TEE support for the MT8195 SoC.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>

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b831e57b16-Jan-2023 Etienne Carriere <etienne.carriere@linaro.org>

plat-stm32mp1: don't register SYSRAM twice when scmi-msg are enabled

Fixes stm32mp1 platform to not register the SCMI shared memory twice
when scmi-msg drivers are enable (CFG_SCMI_MSG_DRIVERS=y) an

plat-stm32mp1: don't register SYSRAM twice when scmi-msg are enabled

Fixes stm32mp1 platform to not register the SCMI shared memory twice
when scmi-msg drivers are enable (CFG_SCMI_MSG_DRIVERS=y) and SCP firmware
SCMI library disabled (CFG_SCMI_SCPFW=n). The faulty fixed referenced
commit introduced this duplicated device memory registration when adding
support for SCP firmware SCMI library where this registration was added
in main.c but not removed from plat-stm32mp1/scmi-server.c.

Before this fix, the debug trace below was printed:
D/TC:0 add_phys_mem:649 Physical mem map overlaps 0x2ffff000

Fixes: 986fccc8150b ("plat-stm32mp1: support building with CFG_SCMI_SCPFW=y")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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16967f6816-Jan-2023 Etienne Carriere <etienne.carriere@linaro.org>

plat-stm32mp1: fix SYSRAM size on stm32mp13 variants

Fixes internal RAM SYSRAM size on STM32MP13 variants that is 128kB.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien

plat-stm32mp1: fix SYSRAM size on stm32mp13 variants

Fixes internal RAM SYSRAM size on STM32MP13 variants that is 128kB.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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3bc3809a13-Jan-2023 Etienne Carriere <etienne.carriere@linaro.org>

core: pta: scmi: fix typo in open session test

Fixes a typo in config switch name CFG_SCMI_MSG_DRIVERS in SCMI PTA
open session function.

Fixes: 7ff454421a8c ("core: pta: scmi: support SCP-firmware

core: pta: scmi: fix typo in open session test

Fixes a typo in config switch name CFG_SCMI_MSG_DRIVERS in SCMI PTA
open session function.

Fixes: 7ff454421a8c ("core: pta: scmi: support SCP-firmware SCMI resources")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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d8f7685a12-Jan-2023 Jerome Forissier <jerome.forissier@linaro.org>

core: log capabilities with INFO level

Use IMSG() to log the capabilities that depend on configuration, which
are: reserved and dynamic shared memory, virtualization and asynchronous
notifications.

core: log capabilities with INFO level

Use IMSG() to log the capabilities that depend on configuration, which
are: reserved and dynamic shared memory, virtualization and asynchronous
notifications.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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7c10274204-Jan-2023 Gatien Chevallier <gatien.chevallier@foss.st.com>

drivers: rstctrl: differentiate error codes if items not found

Differentiates error codes in rstctrl_dt_get_by_name() if reset-names
property does not exist by returning TEE_ERROR_ITEM_NOT_FOUND.
Ad

drivers: rstctrl: differentiate error codes if items not found

Differentiates error codes in rstctrl_dt_get_by_name() if reset-names
property does not exist by returning TEE_ERROR_ITEM_NOT_FOUND.
Add comment for rstctrl_dt_get_by_index() that can now return
TEE_ERROR_ITEM_NOT_FOUND.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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