1# Setup compiler for the core module 2ifeq ($(CFG_ARM64_core),y) 3arch-bits-core := 64 4else 5arch-bits-core := 32 6endif 7CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core)) 8COMPILER_core := $(COMPILER) 9include mk/$(COMPILER_core).mk 10 11# Defines the cc-option macro using the compiler set for the core module 12include mk/cc-option.mk 13 14# Size of emulated TrustZone protected SRAM, 448 kB. 15# Only applicable when paging is enabled. 16CFG_CORE_TZSRAM_EMUL_SIZE ?= 458752 17 18ifneq ($(CFG_LPAE_ADDR_SPACE_SIZE),) 19$(warning Error: CFG_LPAE_ADDR_SPACE_SIZE is not supported any longer) 20$(error Error: Please use CFG_LPAE_ADDR_SPACE_BITS instead) 21endif 22 23CFG_LPAE_ADDR_SPACE_BITS ?= 32 24 25CFG_MMAP_REGIONS ?= 13 26CFG_RESERVED_VASPACE_SIZE ?= (1024 * 1024 * 10) 27 28ifeq ($(CFG_ARM64_core),y) 29ifeq ($(CFG_ARM32_core),y) 30$(error CFG_ARM64_core and CFG_ARM32_core cannot be both 'y') 31endif 32CFG_KERN_LINKER_FORMAT ?= elf64-littleaarch64 33CFG_KERN_LINKER_ARCH ?= aarch64 34# TCR_EL1.IPS needs to be initialized according to the largest physical 35# address that we need to map. 36# Physical address size 37# 32 bits, 4GB. 38# 36 bits, 64GB. 39# (etc.) 40CFG_CORE_ARM64_PA_BITS ?= 32 41$(call force,CFG_WITH_LPAE,y) 42else 43$(call force,CFG_ARM32_core,y) 44CFG_KERN_LINKER_FORMAT ?= elf32-littlearm 45CFG_KERN_LINKER_ARCH ?= arm 46endif 47 48ifeq ($(CFG_TA_FLOAT_SUPPORT),y) 49# Use hard-float for floating point support in user TAs instead of 50# soft-float 51CFG_WITH_VFP ?= y 52ifeq ($(CFG_ARM64_core),y) 53# AArch64 has no fallback to soft-float 54$(call force,CFG_WITH_VFP,y) 55endif 56ifeq ($(CFG_WITH_VFP),y) 57arm64-platform-hard-float-enabled := y 58ifneq ($(CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT),y) 59arm32-platform-hard-float-enabled := y 60endif 61endif 62endif 63 64# Adds protection against CVE-2017-5715 also know as Spectre 65# (https://spectreattack.com) 66# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf 67# Variant 2 68CFG_CORE_WORKAROUND_SPECTRE_BP ?= y 69# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from 70# secure EL0 instead of non-secure world, including mitigation for 71# CVE-2022-23960. 72CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP) 73 74# Adds protection against a tool like Cachegrab 75# (https://github.com/nccgroup/cachegrab), which uses non-secure interrupts 76# to prime and later analyze the L1D, L1I and BTB caches to gain 77# information from secure world execution. 78CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME ?= y 79ifeq ($(CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME),y) 80$(call force,CFG_CORE_WORKAROUND_SPECTRE_BP,y,Required by CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME) 81endif 82 83# Adds workarounds against if ARM core is configured with Non-maskable FIQ 84# (NMFI) support. This is indicated by SCTLR.NMFI being true. NMFI cannot be 85# disabled by software and as it affects atomic context end result will be 86# prohibiting FIQ signal usage in OP-TEE and applying some tweaks to make sure 87# FIQ is enabled in critical places. 88CFG_CORE_WORKAROUND_ARM_NMFI ?= n 89 90CFG_CORE_RWDATA_NOEXEC ?= y 91CFG_CORE_RODATA_NOEXEC ?= n 92ifeq ($(CFG_CORE_RODATA_NOEXEC),y) 93$(call force,CFG_CORE_RWDATA_NOEXEC,y) 94endif 95# 'y' to set the Alignment Check Enable bit in SCTLR/SCTLR_EL1, 'n' to clear it 96CFG_SCTLR_ALIGNMENT_CHECK ?= n 97 98ifeq ($(CFG_CORE_LARGE_PHYS_ADDR),y) 99$(call force,CFG_WITH_LPAE,y) 100endif 101 102# SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1, 103# that is, OP-TEE. 104ifeq ($(CFG_CORE_SEL1_SPMC),y) 105$(call force,CFG_CORE_FFA,y) 106$(call force,CFG_CORE_SEL2_SPMC,n) 107$(call force,CFG_CORE_EL3_SPMC,n) 108endif 109# SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2, 110# that is, the hypervisor sandboxing OP-TEE 111ifeq ($(CFG_CORE_SEL2_SPMC),y) 112$(call force,CFG_CORE_FFA,y) 113$(call force,CFG_CORE_SEL1_SPMC,n) 114$(call force,CFG_CORE_EL3_SPMC,n) 115endif 116# SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that 117# is, in TF-A 118ifeq ($(CFG_CORE_EL3_SPMC),y) 119$(call force,CFG_CORE_FFA,y) 120$(call force,CFG_CORE_SEL2_SPMC,n) 121$(call force,CFG_CORE_SEL1_SPMC,n) 122endif 123 124ifeq ($(CFG_CORE_FFA)-$(CFG_WITH_PAGER),y-y) 125$(error CFG_CORE_FFA and CFG_WITH_PAGER are not compatible) 126endif 127ifeq ($(CFG_GIC),y) 128ifeq ($(CFG_ARM_GICV3),y) 129$(call force,CFG_CORE_IRQ_IS_NATIVE_INTR,y) 130else 131$(call force,CFG_CORE_IRQ_IS_NATIVE_INTR,n) 132endif 133endif 134 135# Selects if IRQ is used to signal native interrupt 136# if CFG_CORE_IRQ_IS_NATIVE_INTR == y: 137# IRQ signals a native interrupt pending 138# FIQ signals a foreign non-secure interrupt or a managed exit pending 139# else: (vice versa) 140# IRQ signals a foreign non-secure interrupt or a managed exit pending 141# FIQ signals a native interrupt pending 142CFG_CORE_IRQ_IS_NATIVE_INTR ?= n 143 144# Unmaps all kernel mode code except the code needed to take exceptions 145# from user space and restore kernel mode mapping again. This gives more 146# strict control over what is accessible while in user mode. 147# Addresses CVE-2017-5715 (aka Meltdown) known to affect Arm Cortex-A75 148CFG_CORE_UNMAP_CORE_AT_EL0 ?= y 149 150# Initialize PMCR.DP to 1 to prohibit cycle counting in secure state, and 151# save/restore PMCR during world switch. 152CFG_SM_NO_CYCLE_COUNTING ?= y 153 154 155# CFG_CORE_ASYNC_NOTIF_GIC_INTID is defined by the platform to some free 156# interrupt. Setting it to a non-zero number enables support for using an 157# Arm-GIC to notify normal world. This config variable should use a value 158# larger the 32 to make it of the type SPI. 159# Note that asynchronous notifactions must be enabled with 160# CFG_CORE_ASYNC_NOTIF=y for this variable to be used. 161CFG_CORE_ASYNC_NOTIF_GIC_INTID ?= 0 162 163ifeq ($(CFG_ARM32_core),y) 164# Configration directive related to ARMv7 optee boot arguments. 165# CFG_PAGEABLE_ADDR: if defined, forces pageable data physical address. 166# CFG_NS_ENTRY_ADDR: if defined, forces NS World physical entry address. 167# CFG_DT_ADDR: if defined, forces Device Tree data physical address. 168endif 169 170# CFG_MAX_CACHE_LINE_SHIFT is used to define platform specific maximum cache 171# line size in address lines. This must cover all inner and outer cache levels. 172# When data is aligned with this and cache operations are performed then those 173# only affect correct data. 174# 175# Default value (6 lines or 64 bytes) should cover most architectures, override 176# this in platform config if different. 177CFG_MAX_CACHE_LINE_SHIFT ?= 6 178 179core-platform-cppflags += -I$(arch-dir)/include 180core-platform-subdirs += \ 181 $(addprefix $(arch-dir)/, kernel crypto mm tee) $(platform-dir) 182 183ifneq ($(CFG_WITH_ARM_TRUSTED_FW),y) 184core-platform-subdirs += $(arch-dir)/sm 185endif 186 187arm64-platform-cppflags += -DARM64=1 -D__LP64__=1 188arm32-platform-cppflags += -DARM32=1 -D__ILP32__=1 189 190platform-cflags-generic ?= -ffunction-sections -fdata-sections -pipe 191platform-aflags-generic ?= -pipe 192 193arm32-platform-aflags += -marm 194 195arm32-platform-cflags-no-hard-float ?= -mfloat-abi=soft 196arm32-platform-cflags-hard-float ?= -mfloat-abi=hard -funsafe-math-optimizations 197arm32-platform-cflags-generic-thumb ?= -mthumb \ 198 -fno-short-enums -fno-common -mno-unaligned-access 199arm32-platform-cflags-generic-arm ?= -marm -fno-omit-frame-pointer -mapcs \ 200 -fno-short-enums -fno-common -mno-unaligned-access 201arm32-platform-aflags-no-hard-float ?= 202 203arm64-platform-cflags-no-hard-float ?= -mgeneral-regs-only 204arm64-platform-cflags-hard-float ?= 205arm64-platform-cflags-generic := -mstrict-align $(call cc-option,-mno-outline-atomics,) 206 207ifeq ($(CFG_MEMTAG),y) 208arm64-platform-cflags += -march=armv8.5-a+memtag 209arm64-platform-aflags += -march=armv8.5-a+memtag 210endif 211 212platform-cflags-optimization ?= -O$(CFG_CC_OPT_LEVEL) 213 214ifeq ($(CFG_DEBUG_INFO),y) 215platform-cflags-debug-info ?= -g3 216platform-aflags-debug-info ?= -g 217endif 218 219core-platform-cflags += $(platform-cflags-optimization) 220core-platform-cflags += $(platform-cflags-generic) 221core-platform-cflags += $(platform-cflags-debug-info) 222 223core-platform-aflags += $(platform-aflags-generic) 224core-platform-aflags += $(platform-aflags-debug-info) 225 226ifeq ($(CFG_CORE_ASLR),y) 227core-platform-cflags += -fpie 228endif 229 230ifeq ($(CFG_CORE_PAUTH),y) 231bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 232endif 233 234ifeq ($(CFG_CORE_BTI),y) 235bp-core-opt := $(call cc-option,-mbranch-protection=bti) 236endif 237 238ifeq (y-y,$(CFG_CORE_PAUTH)-$(CFG_CORE_BTI)) 239bp-core-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 240endif 241 242ifeq (y,$(filter $(CFG_CORE_BTI) $(CFG_CORE_PAUTH),y)) 243ifeq (,$(bp-core-opt)) 244$(error -mbranch-protection not supported) 245endif 246core-platform-cflags += $(bp-core-opt) 247endif 248 249ifeq ($(CFG_ARM64_core),y) 250core-platform-cppflags += $(arm64-platform-cppflags) 251core-platform-cflags += $(arm64-platform-cflags) 252core-platform-cflags += $(arm64-platform-cflags-generic) 253core-platform-cflags += $(arm64-platform-cflags-no-hard-float) 254core-platform-aflags += $(arm64-platform-aflags) 255else 256core-platform-cppflags += $(arm32-platform-cppflags) 257core-platform-cflags += $(arm32-platform-cflags) 258core-platform-cflags += $(arm32-platform-cflags-no-hard-float) 259ifeq ($(CFG_UNWIND),y) 260core-platform-cflags += -funwind-tables 261endif 262ifeq ($(CFG_SYSCALL_FTRACE),y) 263core-platform-cflags += $(arm32-platform-cflags-generic-arm) 264else 265core-platform-cflags += $(arm32-platform-cflags-generic-thumb) 266endif 267core-platform-aflags += $(core_arm32-platform-aflags) 268core-platform-aflags += $(arm32-platform-aflags) 269endif 270 271# Provide default supported-ta-targets if not set by the platform config 272ifeq (,$(supported-ta-targets)) 273supported-ta-targets = ta_arm32 274ifeq ($(CFG_ARM64_core),y) 275supported-ta-targets += ta_arm64 276endif 277endif 278 279ta-targets := $(if $(CFG_USER_TA_TARGETS),$(filter $(supported-ta-targets),$(CFG_USER_TA_TARGETS)),$(supported-ta-targets)) 280unsup-targets := $(filter-out $(ta-targets),$(CFG_USER_TA_TARGETS)) 281ifneq (,$(unsup-targets)) 282$(error CFG_USER_TA_TARGETS contains unsupported value(s): $(unsup-targets). Valid values: $(supported-ta-targets)) 283endif 284 285ifneq ($(filter ta_arm32,$(ta-targets)),) 286# Variables for ta-target/sm "ta_arm32" 287CFG_ARM32_ta_arm32 := y 288arch-bits-ta_arm32 := 32 289ta_arm32-platform-cppflags += $(arm32-platform-cppflags) 290ta_arm32-platform-cflags += $(arm32-platform-cflags) 291ta_arm32-platform-cflags += $(platform-cflags-optimization) 292ta_arm32-platform-cflags += $(platform-cflags-debug-info) 293ta_arm32-platform-cflags += -fpic 294 295# Thumb mode doesn't support function graph tracing due to missing 296# frame pointer support required to trace function call chain. So 297# rather compile in ARM mode if function tracing is enabled. 298ifeq ($(CFG_FTRACE_SUPPORT),y) 299ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-arm) 300else 301ta_arm32-platform-cflags += $(arm32-platform-cflags-generic-thumb) 302endif 303 304ifeq ($(arm32-platform-hard-float-enabled),y) 305ta_arm32-platform-cflags += $(arm32-platform-cflags-hard-float) 306else 307ta_arm32-platform-cflags += $(arm32-platform-cflags-no-hard-float) 308endif 309ifeq ($(CFG_UNWIND),y) 310ta_arm32-platform-cflags += -funwind-tables 311endif 312ta_arm32-platform-aflags += $(platform-aflags-generic) 313ta_arm32-platform-aflags += $(platform-aflags-debug-info) 314ta_arm32-platform-aflags += $(arm32-platform-aflags) 315 316ta_arm32-platform-cxxflags += -fpic 317ta_arm32-platform-cxxflags += $(arm32-platform-cxxflags) 318ta_arm32-platform-cxxflags += $(platform-cflags-optimization) 319ta_arm32-platform-cxxflags += $(platform-cflags-debug-info) 320 321ifeq ($(arm32-platform-hard-float-enabled),y) 322ta_arm32-platform-cxxflags += $(arm32-platform-cflags-hard-float) 323else 324ta_arm32-platform-cxxflags += $(arm32-platform-cflags-no-hard-float) 325endif 326 327ta-mk-file-export-vars-ta_arm32 += CFG_ARM32_ta_arm32 328ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cppflags 329ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cflags 330ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-aflags 331ta-mk-file-export-vars-ta_arm32 += ta_arm32-platform-cxxflags 332 333ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE ?= arm-linux-gnueabihf-_nl_ 334ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE32 ?= $$(CROSS_COMPILE)_nl_ 335ta-mk-file-export-add-ta_arm32 += CROSS_COMPILE_ta_arm32 ?= $$(CROSS_COMPILE32)_nl_ 336ta-mk-file-export-add-ta_arm32 += COMPILER ?= gcc_nl_ 337ta-mk-file-export-add-ta_arm32 += COMPILER_ta_arm32 ?= $$(COMPILER)_nl_ 338ta-mk-file-export-add-ta_arm32 += PYTHON3 ?= python3_nl_ 339endif 340 341ifneq ($(filter ta_arm64,$(ta-targets)),) 342# Variables for ta-target/sm "ta_arm64" 343CFG_ARM64_ta_arm64 := y 344arch-bits-ta_arm64 := 64 345ta_arm64-platform-cppflags += $(arm64-platform-cppflags) 346ta_arm64-platform-cflags += $(arm64-platform-cflags) 347ta_arm64-platform-cflags += $(platform-cflags-optimization) 348ta_arm64-platform-cflags += $(platform-cflags-debug-info) 349ta_arm64-platform-cflags += -fpic 350ta_arm64-platform-cflags += $(arm64-platform-cflags-generic) 351ifeq ($(arm64-platform-hard-float-enabled),y) 352ta_arm64-platform-cflags += $(arm64-platform-cflags-hard-float) 353else 354ta_arm64-platform-cflags += $(arm64-platform-cflags-no-hard-float) 355endif 356ta_arm64-platform-aflags += $(platform-aflags-generic) 357ta_arm64-platform-aflags += $(platform-aflags-debug-info) 358ta_arm64-platform-aflags += $(arm64-platform-aflags) 359 360ta_arm64-platform-cxxflags += -fpic 361ta_arm64-platform-cxxflags += $(platform-cflags-optimization) 362ta_arm64-platform-cxxflags += $(platform-cflags-debug-info) 363 364ifeq ($(CFG_TA_PAUTH),y) 365bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf) 366endif 367 368ifeq ($(CFG_TA_BTI),y) 369bp-ta-opt := $(call cc-option,-mbranch-protection=bti) 370endif 371 372ifeq (y-y,$(CFG_TA_PAUTH)-$(CFG_TA_BTI)) 373bp-ta-opt := $(call cc-option,-mbranch-protection=pac-ret+leaf+bti) 374endif 375 376ifeq (y,$(filter $(CFG_TA_BTI) $(CFG_TA_PAUTH),y)) 377ifeq (,$(bp-ta-opt)) 378$(error -mbranch-protection not supported) 379endif 380ta_arm64-platform-cflags += $(bp-ta-opt) 381endif 382 383ta-mk-file-export-vars-ta_arm64 += CFG_ARM64_ta_arm64 384ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cppflags 385ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cflags 386ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-aflags 387ta-mk-file-export-vars-ta_arm64 += ta_arm64-platform-cxxflags 388 389ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE64 ?= $$(CROSS_COMPILE)_nl_ 390ta-mk-file-export-add-ta_arm64 += CROSS_COMPILE_ta_arm64 ?= $$(CROSS_COMPILE64)_nl_ 391ta-mk-file-export-add-ta_arm64 += COMPILER ?= gcc_nl_ 392ta-mk-file-export-add-ta_arm64 += COMPILER_ta_arm64 ?= $$(COMPILER)_nl_ 393ta-mk-file-export-add-ta_arm64 += PYTHON3 ?= python3_nl_ 394endif 395 396# Set cross compiler prefix for each TA target 397$(foreach sm, $(ta-targets), $(eval CROSS_COMPILE_$(sm) ?= $(CROSS_COMPILE$(arch-bits-$(sm))))) 398 399arm32-sysreg-txt = core/arch/arm/kernel/arm32_sysreg.txt 400arm32-sysregs-$(arm32-sysreg-txt)-h := arm32_sysreg.h 401arm32-sysregs-$(arm32-sysreg-txt)-s := arm32_sysreg.S 402arm32-sysregs += $(arm32-sysreg-txt) 403 404ifeq ($(CFG_ARM_GICV3),y) 405arm32-gicv3-sysreg-txt = core/arch/arm/kernel/arm32_gicv3_sysreg.txt 406arm32-sysregs-$(arm32-gicv3-sysreg-txt)-h := arm32_gicv3_sysreg.h 407arm32-sysregs-$(arm32-gicv3-sysreg-txt)-s := arm32_gicv3_sysreg.S 408arm32-sysregs += $(arm32-gicv3-sysreg-txt) 409endif 410 411arm32-sysregs-out := $(out-dir)/$(sm)/include/generated 412 413define process-arm32-sysreg 414FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 415cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h) 416 417$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-h): $(1) scripts/arm32_sysreg.py 418 @$(cmd-echo-silent) ' GEN $$@' 419 $(q)mkdir -p $$(dir $$@) 420 $(q)scripts/arm32_sysreg.py --guard __$$(arm32-sysregs-$(1)-h) \ 421 < $$< > $$@ 422 423FORCE-GENSRC$(sm): $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 424cleanfiles := $$(cleanfiles) $$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s) 425 426$$(arm32-sysregs-out)/$$(arm32-sysregs-$(1)-s): $(1) scripts/arm32_sysreg.py 427 @$(cmd-echo-silent) ' GEN $$@' 428 $(q)mkdir -p $$(dir $$@) 429 $(q)scripts/arm32_sysreg.py --s_file < $$< > $$@ 430endef #process-arm32-sysreg 431 432$(foreach sr, $(arm32-sysregs), $(eval $(call process-arm32-sysreg,$(sr)))) 433