1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/tpm2_mmio.h> 12 #include <drivers/tpm2_ptp_fifo.h> 13 #include <drivers/tzc400.h> 14 #include <initcall.h> 15 #include <keep.h> 16 #include <kernel/boot.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/notif.h> 20 #include <kernel/panic.h> 21 #include <kernel/spinlock.h> 22 #include <kernel/tee_time.h> 23 #include <mm/core_memprot.h> 24 #include <mm/core_mmu.h> 25 #include <platform_config.h> 26 #include <sm/psci.h> 27 #include <stdint.h> 28 #include <string.h> 29 #include <trace.h> 30 31 static struct gic_data gic_data __maybe_unused __nex_bss; 32 static struct pl011_data console_data __nex_bss; 33 34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 35 #if defined(CFG_DRIVERS_TPM2_MMIO) 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TPM2_BASE, TPM2_REG_SIZE); 37 #endif 38 #if defined(PLATFORM_FLAVOR_fvp) 39 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 40 #endif 41 #if defined(PLATFORM_FLAVOR_qemu_virt) 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 43 #endif 44 #ifdef DRAM0_BASE 45 register_ddr(DRAM0_BASE, DRAM0_SIZE); 46 #endif 47 #ifdef DRAM1_BASE 48 register_ddr(DRAM1_BASE, DRAM1_SIZE); 49 #endif 50 51 #ifdef CFG_GIC 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 54 55 void main_init_gic(void) 56 { 57 #if defined(CFG_WITH_ARM_TRUSTED_FW) 58 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 59 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, 60 GIC_BASE + GICD_OFFSET); 61 #else 62 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 63 #endif 64 itr_init(&gic_data.chip); 65 } 66 67 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 68 void main_secondary_init_gic(void) 69 { 70 gic_cpu_init(&gic_data); 71 } 72 #endif 73 74 void itr_core_handler(void) 75 { 76 gic_it_handle(&gic_data); 77 } 78 #endif /*CFG_GIC*/ 79 80 void console_init(void) 81 { 82 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 83 CONSOLE_BAUDRATE); 84 register_serial_console(&console_data.chip); 85 } 86 87 #if defined(CFG_GIC) && defined(IT_CONSOLE_UART) && \ 88 !defined(CFG_VIRTUALIZATION) && \ 89 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 90 /* 91 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 92 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 93 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 94 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 95 * will hang in EL3 since the interrupt will just be delivered again and 96 * again. 97 */ 98 99 static void read_console(void) 100 { 101 struct serial_chip *cons = &console_data.chip; 102 103 if (!cons->ops->getchar || !cons->ops->have_rx_data) 104 return; 105 106 while (cons->ops->have_rx_data(cons)) { 107 int ch __maybe_unused = cons->ops->getchar(cons); 108 109 DMSG("got 0x%x", ch); 110 } 111 } 112 113 static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused) 114 { 115 if (notif_async_is_started()) { 116 /* 117 * Asynchronous notifications are enabled, lets read from 118 * uart in the bottom half instead. 119 */ 120 itr_disable(IT_CONSOLE_UART); 121 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 122 } else { 123 read_console(); 124 } 125 return ITRR_HANDLED; 126 } 127 128 static struct itr_handler console_itr = { 129 .it = IT_CONSOLE_UART, 130 .flags = ITRF_TRIGGER_LEVEL, 131 .handler = console_itr_cb, 132 }; 133 DECLARE_KEEP_PAGER(console_itr); 134 135 static void atomic_console_notif(struct notif_driver *ndrv __unused, 136 enum notif_event ev __maybe_unused) 137 { 138 DMSG("Asynchronous notifications started, event %d", (int)ev); 139 } 140 DECLARE_KEEP_PAGER(atomic_console_notif); 141 142 static void yielding_console_notif(struct notif_driver *ndrv __unused, 143 enum notif_event ev) 144 { 145 switch (ev) { 146 case NOTIF_EVENT_DO_BOTTOM_HALF: 147 read_console(); 148 itr_enable(IT_CONSOLE_UART); 149 break; 150 case NOTIF_EVENT_STOPPED: 151 DMSG("Asynchronous notifications stopped"); 152 itr_enable(IT_CONSOLE_UART); 153 break; 154 default: 155 EMSG("Unknown event %d", (int)ev); 156 } 157 } 158 159 struct notif_driver console_notif = { 160 .atomic_cb = atomic_console_notif, 161 .yielding_cb = yielding_console_notif, 162 }; 163 164 static TEE_Result init_console_itr(void) 165 { 166 itr_add(&console_itr); 167 itr_enable(IT_CONSOLE_UART); 168 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 169 notif_register_driver(&console_notif); 170 return TEE_SUCCESS; 171 } 172 driver_init(init_console_itr); 173 #endif 174 175 #if defined(CFG_DRIVERS_TPM2_MMIO) 176 static TEE_Result init_tpm2(void) 177 { 178 enum tpm2_result res = TPM2_OK; 179 180 res = tpm2_mmio_init(TPM2_BASE); 181 if (res) { 182 EMSG("Failed to initialize TPM2 MMIO"); 183 return TEE_ERROR_GENERIC; 184 } 185 186 DMSG("TPM2 Chip initialized"); 187 188 return TEE_SUCCESS; 189 } 190 driver_init(init_tpm2); 191 #endif /* defined(CFG_DRIVERS_TPM2_MMIO) */ 192 193 #ifdef CFG_TZC400 194 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 195 196 static TEE_Result init_tzc400(void) 197 { 198 void *va; 199 200 DMSG("Initializing TZC400"); 201 202 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 203 if (!va) { 204 EMSG("TZC400 not mapped"); 205 panic(); 206 } 207 208 tzc_init((vaddr_t)va); 209 tzc_dump_state(); 210 211 return TEE_SUCCESS; 212 } 213 214 service_init(init_tzc400); 215 #endif /*CFG_TZC400*/ 216 217 #if defined(PLATFORM_FLAVOR_qemu_virt) 218 static void release_secondary_early_hpen(size_t pos) 219 { 220 struct mailbox { 221 uint64_t ep; 222 uint64_t hpen[]; 223 } *mailbox; 224 225 if (cpu_mmu_enabled()) 226 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 227 SECRAM_COHERENT_SIZE); 228 else 229 mailbox = (void *)SECRAM_BASE; 230 231 if (!mailbox) 232 panic(); 233 234 mailbox->ep = TEE_LOAD_ADDR; 235 dsb_ishst(); 236 mailbox->hpen[pos] = 1; 237 dsb_ishst(); 238 sev(); 239 } 240 241 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 242 { 243 size_t pos = get_core_pos_mpidr(core_id); 244 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 245 246 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 247 return PSCI_RET_INVALID_PARAMETERS; 248 249 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 250 251 if (core_is_released[pos]) { 252 EMSG("core %zu already released", pos); 253 return PSCI_RET_DENIED; 254 } 255 core_is_released[pos] = true; 256 257 boot_set_core_ns_entry(pos, entry, context_id); 258 release_secondary_early_hpen(pos); 259 260 return PSCI_RET_SUCCESS; 261 } 262 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 263