core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-develo

core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC

core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC-V calling convention, preserve
the hart ID in s0 (callee-saved) to avoid unnecessary
save-restore operations when making function calls.

Also, use temporary registers instead in set_tp, makes
it more consistent with set_sp.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: implement get_aslr_seed() function

Implement the get_aslr_seed() function to provide ASLR
seed generation. Prefer sourcing the seed through the
hardware RNG (using the Zkr extension), a

core: riscv: implement get_aslr_seed() function

Implement the get_aslr_seed() function to provide ASLR
seed generation. Prefer sourcing the seed through the
hardware RNG (using the Zkr extension), and fallback to
platform-specific seed generation when Zkr is unavailable.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: kern.ld.S: add relocation sections for ASLR

Add .rela.dyn and .data.rel.ro sections to support position-independent
code. These sections store the relocation entries needed when ASLR
ra

core: riscv: kern.ld.S: add relocation sections for ASLR

Add .rela.dyn and .data.rel.ro sections to support position-independent
code. These sections store the relocation entries needed when ASLR
randomly maps code and data in memory.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: make boot_mmu_config global and add it into identity_map

Change boot_mmu_config from LOCAL_DATA to DATA to make
it globally accessible. Also, add it into data section
of identity_map.

core: riscv: make boot_mmu_config global and add it into identity_map

Change boot_mmu_config from LOCAL_DATA to DATA to make
it globally accessible. Also, add it into data section
of identity_map.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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riscv: add ELF header definitions

Add RISC-V specific ELF header definitions in a new header
file to support ELF parsing for handling dynamic relocations.

We referred to u-boot/arch/riscv/cpu/start

riscv: add ELF header definitions

Add RISC-V specific ELF header definitions in a new header
file to support ELF parsing for handling dynamic relocations.

We referred to u-boot/arch/riscv/cpu/start.S to obtain the
definitions we need in OP-TEE.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: implement ASLR base address calculation

Implement arch_aslr_base_addr() for RISC-V to compute the ASLR base
address using the provided seed.

The implementation maps addresses across th

core: riscv: implement ASLR base address calculation

Implement arch_aslr_base_addr() for RISC-V to compute the ASLR base
address using the provided seed.

The implementation maps addresses across the full virtual address space:
- When MSB of new based address is set, the address is mapped
to the upper half by extending MSB to 64-bit
- Otherwise, it's mapped to the lower half

This approach utilizes the entire available virtual address space for
ASLR (e.g. 512 GiB for Sv39).

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add tamper event detection configuration for stm32mp257f-ev1

Add and default enable support for the TAMP button present on the
stm32mp257f-ev1 board. It relies on the external tamper 1.

dts: stm32: add tamper event detection configuration for stm32mp257f-ev1

Add and default enable support for the TAMP button present on the
stm32mp257f-ev1 board. It relies on the external tamper 1.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp251.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides

dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp251.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides wakeup capabilities.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add tamper event detection configuration for stm32mp135f-dk

Add and default enable support for the TAMP button present on the
stm32mp135f-dk board. It relies on the external tamper 2.
Se

dts: stm32: add tamper event detection configuration for stm32mp135f-dk

Add and default enable support for the TAMP button present on the
stm32mp135f-dk board. It relies on the external tamper 2.
Set GPIOA6 as secure as it now serve this purpose.

Add and default disable support for a test setup of an active tamper
event detection that is feasible with the GPIO expansion present on the
stm32mp135f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp131.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides

dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp131.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides wakeup capabilities.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add passive tamper sampling configuration for stm32mp15xx-dkx

Add a passive tamper sampling configuration for stm32mp15xx-dkx boards.

Signed-off-by: Gatien Chevallier <gatien.chevallier

dts: stm32: add passive tamper sampling configuration for stm32mp15xx-dkx

Add a passive tamper sampling configuration for stm32mp15xx-dkx boards.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add TAMP interrupt line for tamper events in stm32mp151.dtsi

Add the TAMP interrupt line in the stm32mp151.dtsi for tamper events
to handle the interrupt generation.

Signed-off-by: Gati

dts: stm32: add TAMP interrupt line for tamper events in stm32mp151.dtsi

Add the TAMP interrupt line in the stm32mp151.dtsi for tamper events
to handle the interrupt generation.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_tamp: add tamper events detection support

The anti-tamper detection circuit is used to protect sensitive data
from external attacks. The backup registers, as well as other secrets in

drivers: stm32_tamp: add tamper events detection support

The anti-tamper detection circuit is used to protect sensitive data
from external attacks. The backup registers, as well as other secrets in
the device, are protected by this anti-tamper detection circuit with
some tamper pins and internal tampers. The external tamper pins can
be configured for edge detection, or level detection with or without
filtering, or active tamper which increases the security level by auto
checking that the tamper pins are not externally opened or shorted.

Add support for the device-tree configuration of internal and external
tamper events as well as the list hardware mapped pins with their
associated tamper ID for external tampers.

While there, fix the license for this driver.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add stm32 TAMP support

Add device tree bindings for the TAMP hardware block stm32mpxx
platforms. These bindings permit the description of the configuration
of tamper events.

Signed-off

dt-bindings: add stm32 TAMP support

Add device tree bindings for the TAMP hardware block stm32mpxx
platforms. These bindings permit the description of the configuration
of tamper events.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rtc: add time stamping feature support

Support the time stamping features of the RTC. It is useful to generate
a timestamp whenever a particular event occurs.

Signed-off-by: Gatien C

drivers: stm32_rtc: add time stamping feature support

Support the time stamping features of the RTC. It is useful to generate
a timestamp whenever a particular event occurs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: add stm32_gpio_get_bank_id() helper

Add stm32_gpio_get_bank_id() helper function to get the STM32
GPIO bank ID related to its GPIO chip

Signed-off-by: Gatien Chevallier <gatien

drivers: stm32_gpio: add stm32_gpio_get_bank_id() helper

Add stm32_gpio_get_bank_id() helper function to get the STM32
GPIO bank ID related to its GPIO chip

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp2xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carr

plat-stm32mp2: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp2xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp1xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carr

plat-stm32mp1: conf: default enable CFG_STM32_EXTI

Enable the driver stm32_exti on stm32mp1xx.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI RIF configuration for the stm32mp257f-ev1 board

Add the RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Et

dts: stm32: add EXTI RIF configuration for the stm32mp257f-ev1 board

Add the RIF configuration for the stm32mp257f-ev1 board.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI node in stm32mp251

Add the EXTI support for stm32mp25 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

dts: stm32: update EXTI node in stm32mp151

Update the EXTI support for stm32mp15 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st

dts: stm32: update EXTI node in stm32mp151

Update the EXTI support for stm32mp15 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI node in stm32mp131

Add the EXTI support for stm32mp13 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

drivers: add stm32 EXTI support

The stm32 EXTI peripheral is an interrupt controller that routes
the incoming interrupts to the GIC parent interrupt controller.
The EXTI can trigger the wake-up of t

drivers: add stm32 EXTI support

The stm32 EXTI peripheral is an interrupt controller that routes
the incoming interrupts to the GIC parent interrupt controller.
The EXTI can trigger the wake-up of the system on the incoming
interrupts.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt: add set_wake for power-management wake-on on interrupt

For interrupt controllers that can handle power-management wake-up
when receiving an interrupt, add the operation set_wake().

core: interrupt: add set_wake for power-management wake-on on interrupt

For interrupt controllers that can handle power-management wake-up
when receiving an interrupt, add the operation set_wake().

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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