1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2018-2025, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <drivers/clk.h> 7 #include <drivers/clk_dt.h> 8 #include <drivers/rtc.h> 9 #include <drivers/stm32_rif.h> 10 #include <drivers/stm32_rtc.h> 11 #include <io.h> 12 #include <keep.h> 13 #include <kernel/dt.h> 14 #include <kernel/dt_driver.h> 15 #include <kernel/interrupt.h> 16 #include <kernel/notif.h> 17 #include <kernel/panic.h> 18 #include <kernel/spinlock.h> 19 #include <libfdt.h> 20 #include <mm/core_memprot.h> 21 22 /* 23 * Registers 24 */ 25 #define RTC_TR U(0x00) 26 #define RTC_DR U(0x04) 27 #define RTC_SSR U(0x08) 28 #define RTC_ICSR U(0x0C) 29 #define RTC_PRER U(0x10) 30 #define RTC_WUTR U(0x14) 31 #define RTC_CR U(0x18) 32 #define RTC_PRIVCFGR U(0x1C) 33 /* RTC_SMCR is linked to RTC3v1_2 */ 34 #define RTC_SMCR U(0x20) 35 /* RTC_SECCFGR is linked to RTC3v3_2 and above */ 36 #define RTC_SECCFGR U(0x20) 37 #define RTC_WPR U(0x24) 38 #define RTC_CALR U(0x28) 39 #define RTC_SHIFTR U(0x2C) 40 #define RTC_TSTR U(0x30) 41 #define RTC_TSDR U(0x34) 42 #define RTC_TSSSR U(0x38) 43 #define RTC_ALRMAR U(0x40) 44 #define RTC_ALRMASSR U(0x44) 45 #define RTC_ALRMBR U(0x48) 46 #define RTC_ALRMBSSR U(0x4C) 47 #define RTC_SR U(0x50) 48 #define RTC_SCR U(0x5C) 49 #define RTC_OR U(0x60) 50 #define RTC_CIDCFGR(x) (U(0x80) + U(0x4) * (x)) 51 52 #define RTC_TR_SU_MASK GENMASK_32(3, 0) 53 #define RTC_TR_ST_MASK GENMASK_32(6, 4) 54 #define RTC_TR_ST_SHIFT U(4) 55 #define RTC_TR_MNU_MASK GENMASK_32(11, 8) 56 #define RTC_TR_MNU_SHIFT U(8) 57 #define RTC_TR_MNT_MASK GENMASK_32(14, 12) 58 #define RTC_TR_MNT_SHIFT U(12) 59 #define RTC_TR_HU_MASK GENMASK_32(19, 16) 60 #define RTC_TR_HU_SHIFT U(16) 61 #define RTC_TR_HT_MASK GENMASK_32(21, 20) 62 #define RTC_TR_HT_SHIFT U(20) 63 #define RTC_TR_PM BIT(22) 64 65 #define RTC_DR_DU_MASK GENMASK_32(3, 0) 66 #define RTC_DR_DT_MASK GENMASK_32(5, 4) 67 #define RTC_DR_DT_SHIFT U(4) 68 #define RTC_DR_MU_MASK GENMASK_32(11, 8) 69 #define RTC_DR_MU_SHIFT U(8) 70 #define RTC_DR_MT_MASK BIT(12) 71 #define RTC_DR_MT_SHIFT U(12) 72 #define RTC_DR_WDU_MASK GENMASK_32(15, 13) 73 #define RTC_DR_WDU_SHIFT U(13) 74 #define RTC_DR_YU_MASK GENMASK_32(19, 16) 75 #define RTC_DR_YU_SHIFT U(16) 76 #define RTC_DR_YT_MASK GENMASK_32(23, 20) 77 #define RTC_DR_YT_SHIFT U(20) 78 79 #define RTC_SSR_SS_MASK GENMASK_32(15, 0) 80 81 #define RTC_ICSR_RSF BIT(5) 82 #define RTC_ICSR_INITF BIT(6) 83 #define RTC_ICSR_INIT BIT(7) 84 85 #define RTC_PRER_PREDIV_S_SHIFT U(0) 86 #define RTC_PRER_PREDIV_S_MASK GENMASK_32(14, 0) 87 #define RTC_PRER_PREDIV_A_SHIFT U(16) 88 #define RTC_PRER_PREDIV_A_MASK GENMASK_32(22, 16) 89 90 #define RTC_CR_BYPSHAD BIT(5) 91 #define RTC_CR_BYPSHAD_SHIFT U(5) 92 #define RTC_CR_FMT BIT(6) 93 #define RTC_CR_ALRAE BIT(8) 94 #define RTC_CR_ALRAIE BIT(12) 95 #define RTC_CR_TAMPTS BIT(25) 96 97 #define RTC_PRIVCFGR_VALUES GENMASK_32(3, 0) 98 #define RTC_PRIVCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 99 #define RTC_PRIVCFGR_SHIFT U(9) 100 #define RTC_PRIVCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 101 #define RTC_PRIVCFGR_FULL_PRIV BIT(15) 102 103 #define RTC_SMCR_TS_DPROT BIT(3) 104 105 #define RTC_SECCFGR_VALUES GENMASK_32(3, 0) 106 #define RTC_SECCFGR_TS_SEC BIT(3) 107 #define RTC_SECCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 108 #define RTC_SECCFGR_SHIFT U(9) 109 #define RTC_SECCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 110 #define RTC_SECCFGR_FULL_SEC BIT(15) 111 112 #define RTC_WPR_KEY1 U(0xCA) 113 #define RTC_WPR_KEY2 U(0x53) 114 #define RTC_WPR_KEY_LOCK U(0xFF) 115 116 #define RTC_TSDR_MU_MASK GENMASK_32(11, 8) 117 #define RTC_TSDR_MU_SHIFT U(8) 118 #define RTC_TSDR_DT_MASK GENMASK_32(5, 4) 119 #define RTC_TSDR_DT_SHIFT U(4) 120 #define RTC_TSDR_DU_MASK GENMASK_32(3, 0) 121 #define RTC_TSDR_DU_SHIFT U(0) 122 123 #define RTC_ALRMXR_SEC_UNITS_MASK GENMASK_32(3, 0) 124 #define RTC_ALRMXR_SEC_UNITS_SHIFT U(0) 125 #define RTC_ALRMXR_SEC_TENS_MASK GENMASK_32(6, 4) 126 #define RTC_ALRMXR_SEC_TENS_SHIFT U(4) 127 #define RTC_ALRMXR_SEC_MASK BIT(7) 128 #define RTC_ALRMXR_MIN_UNITS_MASK GENMASK_32(11, 8) 129 #define RTC_ALRMXR_MIN_UNITS_SHIFT U(8) 130 #define RTC_ALRMXR_MIN_TENS_MASK GENMASK_32(14, 12) 131 #define RTC_ALRMXR_MIN_TENS_SHIFT U(12) 132 #define RTC_ALRMXR_MIN_MASK BIT(15) 133 #define RTC_ALRMXR_HOUR_UNITS_MASK GENMASK_32(19, 16) 134 #define RTC_ALRMXR_HOUR_UNITS_SHIFT U(16) 135 #define RTC_ALRMXR_HOUR_TENS_MASK GENMASK_32(21, 20) 136 #define RTC_ALRMXR_HOUR_TENS_SHIFT U(20) 137 #define RTC_ALRMXR_PM BIT(22) 138 #define RTC_ALRMXR_HOUR_MASK BIT(23) 139 #define RTC_ALRMXR_DATE_UNITS_MASK GENMASK_32(27, 24) 140 #define RTC_ALRMXR_DATE_UNITS_SHIFT U(24) 141 #define RTC_ALRMXR_DATE_TENS_MASK GENMASK_32(29, 28) 142 #define RTC_ALRMXR_DATE_TENS_SHIFT U(28) 143 144 #define RTC_SR_ALRAF BIT(0) 145 #define RTC_SR_TSF BIT(3) 146 #define RTC_SR_TSOVF BIT(4) 147 148 #define RTC_SCR_CALRAF BIT(0) 149 #define RTC_SCR_CTSF BIT(3) 150 #define RTC_SCR_CTSOVF BIT(4) 151 152 #define RTC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 153 #define RTC_CIDCFGR_SCID_MASK_SHIFT U(4) 154 #define RTC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 155 RTC_CIDCFGR_SCID_MASK) 156 157 /* 158 * RIF miscellaneous 159 */ 160 #define RTC_NB_RIF_RESOURCES U(6) 161 162 #define RTC_RIF_FULL_PRIVILEGED U(0x3F) 163 #define RTC_RIF_FULL_SECURED U(0x3F) 164 165 #define RTC_NB_MAX_CID_SUPPORTED U(7) 166 167 /* 168 * Driver miscellaneous 169 */ 170 #define RTC_RES_TIMESTAMP U(3) 171 #define RTC_RES_CALIBRATION U(4) 172 #define RTC_RES_INITIALIZATION U(5) 173 174 #define RTC_FLAGS_READ_TWICE BIT(0) 175 176 #define TIMEOUT_US_RTC_SHADOW U(10000) 177 #define TIMEOUT_US_RTC_GENERIC U(100000) 178 179 #define YEAR_REF ULL(2000) 180 #define YEAR_MAX (YEAR_REF + ULL(99)) 181 182 struct rtc_compat { 183 bool has_seccfgr; 184 bool has_rif_support; 185 }; 186 187 /* 188 * struct rtc_device - RTC device data 189 * @base: RTC IOMEM base address 190 * @compat: RTC compatible data 191 * @pclk: RTC bus clock 192 * @rtc_ck: RTC kernel clock 193 * @conf_data: RTC RIF configuration data, when supported 194 * @nb_res: Number of protectible RTC resources 195 * @ts_lock: Lock used for time stamping events handling 196 * @flags: RTC driver flags 197 * @is_secured: True if the RTC is fully secured 198 * @itr_chip: Interrupt chip 199 * @itr_num: Interrupt number 200 * @itr_handler: Interrupt handler 201 * @notif_id: Notification ID 202 * @wait_alarm_return_status: Status of the wait alarm thread 203 */ 204 struct rtc_device { 205 struct io_pa_va base; 206 const struct rtc_compat *compat; 207 struct clk *pclk; 208 struct clk *rtc_ck; 209 struct rif_conf_data *conf_data; 210 unsigned int nb_res; 211 unsigned int ts_lock; 212 uint8_t flags; 213 bool is_secured; 214 struct itr_chip *itr_chip; 215 size_t itr_num; 216 struct itr_handler *itr_handler; 217 uint32_t notif_id; 218 enum rtc_wait_alarm_status wait_alarm_return_status; 219 }; 220 221 /* Expect a single RTC instance */ 222 static struct rtc_device rtc_dev; 223 224 static vaddr_t get_base(void) 225 { 226 assert(rtc_dev.base.pa); 227 228 return io_pa_or_va(&rtc_dev.base, 1); 229 } 230 231 static void stm32_rtc_write_unprotect(void) 232 { 233 vaddr_t rtc_base = get_base(); 234 235 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY1); 236 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY2); 237 } 238 239 static void stm32_rtc_write_protect(void) 240 { 241 vaddr_t rtc_base = get_base(); 242 243 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY_LOCK); 244 } 245 246 static bool stm32_rtc_get_bypshad(void) 247 { 248 return io_read32(get_base() + RTC_CR) & RTC_CR_BYPSHAD; 249 } 250 251 /* Get the subsecond value. */ 252 static uint32_t stm32_rtc_get_subsecond(uint32_t ssr) 253 { 254 uint32_t prediv_s = io_read32(get_base() + RTC_PRER) & 255 RTC_PRER_PREDIV_S_MASK; 256 257 return prediv_s - ssr; 258 } 259 260 /* 261 * Get the subsecond scale. 262 * 263 * Number of subseconds in a second is linked to RTC PREDIV_S value. 264 * The higher PREDIV_S is, the more subsecond is precise. 265 */ 266 static uint32_t stm32_rtc_get_subsecond_scale(void) 267 { 268 return (io_read32(get_base() + RTC_PRER) & RTC_PRER_PREDIV_S_MASK) + 1; 269 } 270 271 static bool cid1_has_access(unsigned int resource) 272 { 273 uint32_t cidcfgr = io_read32(get_base() + RTC_CIDCFGR(resource)); 274 275 return !(cidcfgr & _CIDCFGR_CFEN) || 276 get_field_u32(cidcfgr, RTC_CIDCFGR_SCID_MASK) == RIF_CID1; 277 } 278 279 static TEE_Result check_rif_config(void) 280 { 281 if (!cid1_has_access(RTC_RES_TIMESTAMP) || 282 !cid1_has_access(RTC_RES_CALIBRATION) || 283 !cid1_has_access(RTC_RES_INITIALIZATION)) 284 return TEE_ERROR_ACCESS_DENIED; 285 286 return TEE_SUCCESS; 287 } 288 289 static void apply_rif_config(bool is_tdcid) 290 { 291 vaddr_t base = get_base(); 292 unsigned int shifted_values = 0; 293 uint32_t seccfgr = 0; 294 uint32_t privcfgr = 0; 295 uint32_t access_mask_reg = 0; 296 unsigned int i = 0; 297 298 if (!rtc_dev.conf_data) 299 return; 300 301 /* Build access mask for RTC_SECCFGR and RTC_PRIVCFGR */ 302 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 303 if (rtc_dev.conf_data->access_mask[0] & BIT(i)) { 304 if (i <= RTC_RES_TIMESTAMP) 305 access_mask_reg |= BIT(i); 306 else 307 access_mask_reg |= BIT(i) << RTC_SECCFGR_SHIFT; 308 } 309 } 310 311 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 312 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 313 continue; 314 315 /* 316 * When TDCID, OP-TEE should be the one to set the CID filtering 317 * configuration. Clearing previous configuration prevents 318 * undesired events during the only legitimate configuration. 319 */ 320 if (is_tdcid) 321 io_clrbits32(base + RTC_CIDCFGR(i), 322 RTC_CIDCFGR_CONF_MASK); 323 } 324 325 /* Security RIF configuration */ 326 seccfgr = rtc_dev.conf_data->sec_conf[0]; 327 328 /* Check if all resources must be secured */ 329 if (seccfgr == RTC_RIF_FULL_SECURED) { 330 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_FULL_SEC); 331 rtc_dev.is_secured = true; 332 333 if (!(io_read32(base + RTC_SECCFGR) & RTC_SECCFGR_FULL_SEC)) 334 panic("Bad RTC seccfgr configuration"); 335 } 336 337 /* Shift some values to align with the register */ 338 shifted_values = SHIFT_U32(seccfgr & RTC_SECCFGR_VALUES_TO_SHIFT, 339 RTC_SECCFGR_SHIFT); 340 seccfgr = (seccfgr & RTC_SECCFGR_VALUES) + shifted_values; 341 342 io_clrsetbits32(base + RTC_SECCFGR, 343 RTC_SECCFGR_MASK & access_mask_reg, seccfgr); 344 345 /* Privilege RIF configuration */ 346 privcfgr = rtc_dev.conf_data->priv_conf[0]; 347 348 /* Check if all resources must be privileged */ 349 if (privcfgr == RTC_RIF_FULL_PRIVILEGED) { 350 io_setbits32(base + RTC_PRIVCFGR, RTC_PRIVCFGR_FULL_PRIV); 351 352 if (!(io_read32(base + RTC_PRIVCFGR) & RTC_PRIVCFGR_FULL_PRIV)) 353 panic("Bad RTC privcfgr configuration"); 354 } 355 356 /* Shift some values to align with the register */ 357 shifted_values = SHIFT_U32(privcfgr & RTC_PRIVCFGR_VALUES_TO_SHIFT, 358 RTC_PRIVCFGR_SHIFT); 359 privcfgr = (privcfgr & RTC_PRIVCFGR_VALUES) + shifted_values; 360 361 io_clrsetbits32(base + RTC_PRIVCFGR, 362 RTC_PRIVCFGR_MASK & access_mask_reg, privcfgr); 363 364 if (!is_tdcid) 365 return; 366 367 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 368 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 369 continue; 370 /* 371 * When at least one resource has CID filtering enabled, 372 * the RTC_PRIVCFGR_FULL_PRIV and RTC_SECCFGR_FULL_SEC bits are 373 * cleared. 374 */ 375 io_clrsetbits32(base + RTC_CIDCFGR(i), 376 RTC_CIDCFGR_CONF_MASK, 377 rtc_dev.conf_data->cid_confs[i]); 378 } 379 } 380 381 static void stm32_rtc_clear_events(uint32_t flags) 382 { 383 io_write32(get_base() + RTC_SCR, flags); 384 } 385 386 static enum itr_return stm32_rtc_it_handler(struct itr_handler *h __unused) 387 { 388 vaddr_t rtc_base = get_base(); 389 uint32_t status = io_read32(rtc_base + RTC_SR); 390 uint32_t cr = io_read32(rtc_base + RTC_CR); 391 392 if ((status & RTC_SR_ALRAF) && (cr & RTC_CR_ALRAIE)) { 393 DMSG("Alarm occurred"); 394 /* Clear event's flags */ 395 stm32_rtc_clear_events(RTC_SCR_CALRAF); 396 /* 397 * Notify the caller of 'stm32_rtc_wait_alarm' to re-schedule 398 * the calling thread. 399 */ 400 notif_send_async(rtc_dev.notif_id, 0); 401 } 402 403 return ITRR_HANDLED; 404 } 405 DECLARE_KEEP_PAGER(stm32_rtc_it_handler); 406 407 static TEE_Result parse_dt(const void *fdt, int node) 408 { 409 TEE_Result res = TEE_ERROR_GENERIC; 410 const fdt32_t *cuint = NULL; 411 size_t reg_size = 0; 412 unsigned int i = 0; 413 int lenp = 0; 414 415 if (fdt_reg_info(fdt, node, &rtc_dev.base.pa, ®_size)) 416 panic(); 417 418 io_pa_or_va(&rtc_dev.base, reg_size); 419 assert(rtc_dev.base.va); 420 421 res = clk_dt_get_by_name(fdt, node, "pclk", &rtc_dev.pclk); 422 if (res) 423 return res; 424 425 res = clk_dt_get_by_name(fdt, node, "rtc_ck", &rtc_dev.rtc_ck); 426 if (res) 427 return res; 428 429 if (IS_ENABLED(CFG_RTC_PTA) && IS_ENABLED(CFG_DRIVERS_RTC)) { 430 res = interrupt_dt_get(fdt, node, &rtc_dev.itr_chip, 431 &rtc_dev.itr_num); 432 if (res) 433 return res; 434 res = interrupt_create_handler(rtc_dev.itr_chip, 435 rtc_dev.itr_num, 436 stm32_rtc_it_handler, 437 &rtc_dev, 0, 438 &rtc_dev.itr_handler); 439 if (res) 440 return res; 441 } 442 443 if (!rtc_dev.compat->has_rif_support) 444 return TEE_SUCCESS; 445 446 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 447 if (!cuint) { 448 DMSG("No RIF configuration available"); 449 return TEE_SUCCESS; 450 } 451 452 rtc_dev.conf_data = calloc(1, sizeof(*rtc_dev.conf_data)); 453 if (!rtc_dev.conf_data) 454 panic(); 455 456 rtc_dev.nb_res = (unsigned int)(lenp / sizeof(uint32_t)); 457 assert(rtc_dev.nb_res <= RTC_NB_RIF_RESOURCES); 458 459 rtc_dev.conf_data->cid_confs = calloc(RTC_NB_RIF_RESOURCES, 460 sizeof(uint32_t)); 461 rtc_dev.conf_data->sec_conf = calloc(1, sizeof(uint32_t)); 462 rtc_dev.conf_data->priv_conf = calloc(1, sizeof(uint32_t)); 463 rtc_dev.conf_data->access_mask = calloc(1, sizeof(uint32_t)); 464 if (!rtc_dev.conf_data->cid_confs || !rtc_dev.conf_data->sec_conf || 465 !rtc_dev.conf_data->priv_conf || !rtc_dev.conf_data->access_mask) 466 panic("Not enough memory capacity for RTC RIF config"); 467 468 for (i = 0; i < rtc_dev.nb_res; i++) 469 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), rtc_dev.conf_data, 470 RTC_NB_RIF_RESOURCES); 471 472 return TEE_SUCCESS; 473 } 474 475 static TEE_Result stm32_rtc_enter_init_mode(void) 476 { 477 vaddr_t base = get_base(); 478 uint32_t icsr = io_read32(base + RTC_ICSR); 479 uint32_t value = 0; 480 481 if (!(icsr & RTC_ICSR_INITF)) { 482 icsr |= RTC_ICSR_INIT; 483 io_write32(base + RTC_ICSR, icsr); 484 485 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 486 value & RTC_ICSR_INITF, 487 10, TIMEOUT_US_RTC_GENERIC)) 488 return TEE_ERROR_BUSY; 489 } 490 491 return TEE_SUCCESS; 492 } 493 494 static TEE_Result stm32_rtc_exit_init_mode(void) 495 { 496 vaddr_t base = get_base(); 497 uint32_t value = 0; 498 499 io_clrbits32(base + RTC_ICSR, RTC_ICSR_INIT); 500 dsb(); 501 502 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 503 504 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 505 value & RTC_ICSR_RSF, 10, 506 TIMEOUT_US_RTC_GENERIC)) 507 return TEE_ERROR_BUSY; 508 509 return TEE_SUCCESS; 510 } 511 512 static void stm32_rtc_to_tm(uint32_t ssr, uint32_t tr, uint32_t dr, 513 struct optee_rtc_time *tm) 514 { 515 tm->tm_hour = ((tr & RTC_TR_HT_MASK) >> RTC_TR_HT_SHIFT) * 10 + 516 ((tr & RTC_TR_HU_MASK) >> RTC_TR_HU_SHIFT); 517 518 if (tr & RTC_TR_PM) 519 tm->tm_hour += 12; 520 521 tm->tm_ms = (stm32_rtc_get_subsecond(ssr) * MS_PER_SEC) / 522 stm32_rtc_get_subsecond_scale(); 523 524 tm->tm_sec = ((tr & RTC_TR_ST_MASK) >> RTC_TR_ST_SHIFT) * 10 + 525 (tr & RTC_TR_SU_MASK); 526 527 tm->tm_min = ((tr & RTC_TR_MNT_MASK) >> RTC_TR_MNT_SHIFT) * 10 + 528 ((tr & RTC_TR_MNU_MASK) >> RTC_TR_MNU_SHIFT); 529 530 tm->tm_wday = ((dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT) % 7; 531 532 tm->tm_mday = ((dr & RTC_DR_DT_MASK) >> RTC_DR_DT_SHIFT) * 10 + 533 (dr & RTC_DR_DU_MASK); 534 535 tm->tm_mon = ((dr & RTC_DR_MT_MASK) >> RTC_DR_MT_SHIFT) * 10 + 536 ((dr & RTC_DR_MU_MASK) >> RTC_DR_MU_SHIFT) - 1; 537 538 tm->tm_year = ((dr & RTC_DR_YT_MASK) >> RTC_DR_YT_SHIFT) * 10 + 539 ((dr & RTC_DR_YU_MASK) >> RTC_DR_YU_SHIFT) + YEAR_REF; 540 } 541 542 static TEE_Result stm32_rtc_init(void) 543 { 544 uint32_t pred_a_max = RTC_PRER_PREDIV_A_MASK >> RTC_PRER_PREDIV_A_SHIFT; 545 uint32_t pred_s_max = RTC_PRER_PREDIV_S_MASK >> RTC_PRER_PREDIV_S_SHIFT; 546 unsigned long rate = clk_get_rate(rtc_dev.rtc_ck); 547 TEE_Result res = TEE_ERROR_GENERIC; 548 vaddr_t base = get_base(); 549 uint32_t pred_a = 0; 550 uint32_t pred_s = 0; 551 uint32_t prer = io_read32(base + RTC_PRER); 552 uint32_t cr = io_read32(base + RTC_CR); 553 554 if (rate > (pred_a_max + 1) * (pred_s_max + 1)) 555 panic("rtc_ck rate is too high"); 556 557 if (cr & RTC_CR_FMT && !IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) 558 return TEE_SUCCESS; 559 560 if (IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) { 561 /* 562 * Compute the prescaler values whom divides the clock in order 563 * to get a * 1 Hz output by maximizing accuracy 564 * (maximizing PREDIV_S). 565 */ 566 for (pred_a = 0; pred_a <= pred_a_max; pred_a++) { 567 pred_s = (rate / (pred_a + 1)) - 1; 568 if (pred_s <= pred_s_max && 569 ((pred_s + 1) * (pred_a + 1)) == rate) 570 break; 571 } 572 573 /* 574 * 1 Hz output not possible, give priority to RTC power 575 * consumption by choosing the higher possible value for 576 * prediv_a 577 */ 578 if (pred_s > pred_s_max || pred_a > pred_a_max) { 579 pred_a = pred_a_max; 580 pred_s = (rate / (pred_a + 1)) - 1; 581 582 DMSG("rtc_ck is %s", 583 (rate < ((pred_a + 1) * (pred_s + 1))) ? 584 "fast" : "slow"); 585 } 586 587 prer &= RTC_PRER_PREDIV_S_MASK | RTC_PRER_PREDIV_A_MASK; 588 pred_s = SHIFT_U32(pred_s, RTC_PRER_PREDIV_S_SHIFT) & 589 RTC_PRER_PREDIV_S_MASK; 590 pred_a = SHIFT_U32(pred_a, RTC_PRER_PREDIV_A_SHIFT) & 591 RTC_PRER_PREDIV_A_MASK; 592 593 /* Return if there is nothing to initialize */ 594 if (cr & RTC_CR_FMT && prer == (pred_s | pred_a)) 595 return TEE_SUCCESS; 596 } 597 598 stm32_rtc_write_unprotect(); 599 600 res = stm32_rtc_enter_init_mode(); 601 if (res) { 602 EMSG("Can't enter init mode. Fail to initialize RTC."); 603 stm32_rtc_write_protect(); 604 return res; 605 } 606 607 if (IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) { 608 io_write32(base + RTC_PRER, pred_s); 609 io_write32(base + RTC_PRER, pred_a | pred_s); 610 } 611 612 /* Force 24h time format */ 613 cr &= ~RTC_CR_FMT; 614 io_write32(base + RTC_CR, cr); 615 616 res = stm32_rtc_exit_init_mode(); 617 if (res) 618 EMSG("Can't exit init mode. Fail to initialize RTC."); 619 620 stm32_rtc_write_protect(); 621 622 return res; 623 } 624 625 static TEE_Result stm32_rtc_get_time(struct rtc *rtc __unused, 626 struct optee_rtc_time *tm) 627 { 628 vaddr_t base = get_base(); 629 uint32_t ssr = 0; 630 uint32_t dr = 0; 631 uint32_t tr = 0; 632 633 if (!stm32_rtc_get_bypshad()) { 634 uint32_t icsr = 0; 635 636 /* Wait calendar registers are ready */ 637 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 638 639 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, icsr, 640 icsr & RTC_ICSR_RSF, 0, 641 TIMEOUT_US_RTC_SHADOW)) 642 panic(); 643 } 644 645 /* 646 * In our RTC we start : 647 * - year at 0 648 * - month at 1 649 * - day at 1 650 * - weekday at Monday = 1 651 * Change month value so it becomes 0=January, 1 = February, ... 652 * Change week day value so it becomes 0=Sunday, 1 = Monday, ... 653 */ 654 655 ssr = io_read32(base + RTC_SSR); 656 tr = io_read32(base + RTC_TR); 657 dr = io_read32(base + RTC_DR); 658 659 stm32_rtc_to_tm(ssr, tr, dr, tm); 660 661 return TEE_SUCCESS; 662 } 663 664 static TEE_Result stm32_rtc_set_time(struct rtc *rtc, struct optee_rtc_time *tm) 665 { 666 TEE_Result res = TEE_ERROR_GENERIC; 667 vaddr_t rtc_base = get_base(); 668 uint32_t tr = 0; 669 uint32_t dr = 0; 670 671 /* 672 * In our RTC we start : 673 * - year at 0 674 * - month at 1 675 * - day at 1 676 * - weekday at Monday = 1 677 * Change month value so it becomes 1=January, 2 = February, ... 678 * Change week day value so it becomes 7=Sunday, 1 = Monday, ... 679 */ 680 tr = ((tm->tm_sec % 10) & RTC_TR_SU_MASK) | 681 (SHIFT_U32(tm->tm_sec / 10, RTC_TR_ST_SHIFT) & RTC_TR_ST_MASK) | 682 (SHIFT_U32(tm->tm_min % 10, RTC_TR_MNU_SHIFT) & RTC_TR_MNU_MASK) | 683 (SHIFT_U32(tm->tm_min / 10, RTC_TR_MNT_SHIFT) & RTC_TR_MNT_MASK) | 684 (SHIFT_U32(tm->tm_hour % 10, RTC_TR_HU_SHIFT) & RTC_TR_HU_MASK) | 685 (SHIFT_U32(tm->tm_hour / 10, RTC_TR_HT_SHIFT) & RTC_TR_HT_MASK); 686 687 dr = ((tm->tm_mday % 10) & RTC_DR_DU_MASK) | 688 (SHIFT_U32(tm->tm_mday / 10, RTC_DR_DT_SHIFT) & RTC_DR_DT_MASK) | 689 (SHIFT_U32((tm->tm_mon + 1) % 10, RTC_DR_MU_SHIFT) & 690 RTC_DR_MU_MASK) | 691 (SHIFT_U32((tm->tm_mon + 1) / 10, RTC_DR_MT_SHIFT) & 692 RTC_DR_MT_MASK) | 693 (SHIFT_U32(tm->tm_wday ? tm->tm_wday : 7, RTC_DR_WDU_SHIFT) & 694 RTC_DR_WDU_MASK) | 695 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) % 10, 696 RTC_DR_YU_SHIFT) & RTC_DR_YU_MASK) | 697 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) / 10, 698 RTC_DR_YT_SHIFT) & RTC_DR_YT_MASK); 699 700 stm32_rtc_write_unprotect(); 701 702 res = stm32_rtc_enter_init_mode(); 703 if (res) 704 goto end; 705 706 io_write32(rtc_base + RTC_TR, tr); 707 io_write32(rtc_base + RTC_DR, dr); 708 709 res = stm32_rtc_exit_init_mode(); 710 end: 711 stm32_rtc_write_protect(); 712 713 return res; 714 } 715 716 TEE_Result stm32_rtc_get_timestamp(struct optee_rtc_time *tm) 717 { 718 vaddr_t base = get_base(); 719 uint32_t exceptions = 0; 720 uint32_t value = 0; 721 uint32_t ssr = 0; 722 uint32_t dr = 0; 723 uint32_t tr = 0; 724 725 exceptions = cpu_spin_lock_xsave(&rtc_dev.ts_lock); 726 727 if (IO_READ32_POLL_TIMEOUT(base + RTC_SR, value, 728 value & RTC_SR_TSF, 729 10, TIMEOUT_US_RTC_GENERIC)) { 730 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions); 731 return TEE_ERROR_NO_DATA; 732 } 733 734 ssr = io_read32(base + RTC_TSSSR); 735 tr = io_read32(base + RTC_TSTR); 736 dr = io_read32(base + RTC_TSDR); 737 738 io_setbits32(base + RTC_SCR, RTC_SCR_CTSF); 739 740 /* Tamper event overflow detection */ 741 if (io_read32(base + RTC_SR) & RTC_SR_TSOVF) { 742 io_setbits32(base + RTC_SCR, RTC_SCR_CTSOVF); 743 DMSG("A timestamp event occurred while handling current event"); 744 } 745 746 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions); 747 748 stm32_rtc_to_tm(ssr, tr, dr, tm); 749 750 /* No year timestamp available */ 751 tm->tm_year = 0; 752 753 return TEE_SUCCESS; 754 } 755 756 TEE_Result stm32_rtc_set_tamper_timestamp(void) 757 { 758 vaddr_t base = get_base(); 759 760 stm32_rtc_write_unprotect(); 761 762 /* Secure Timestamp bit */ 763 if (!rtc_dev.compat->has_seccfgr) { 764 /* Inverted logic */ 765 io_clrbits32(base + RTC_SMCR, RTC_SMCR_TS_DPROT); 766 } else { 767 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_TS_SEC); 768 } 769 770 /* Enable tamper timestamper */ 771 io_setbits32(base + RTC_CR, RTC_CR_TAMPTS); 772 773 stm32_rtc_write_protect(); 774 775 return TEE_SUCCESS; 776 } 777 778 TEE_Result stm32_rtc_is_timestamp_enabled(bool *ret) 779 { 780 *ret = io_read32(get_base() + RTC_CR) & RTC_CR_TAMPTS; 781 782 return TEE_SUCCESS; 783 } 784 785 TEE_Result stm32_rtc_driver_is_initialized(void) 786 { 787 if (rtc_dev.pclk) 788 return TEE_SUCCESS; 789 790 return TEE_ERROR_DEFER_DRIVER_INIT; 791 } 792 793 static TEE_Result stm32_rtc_read_alarm(struct rtc *rtc, 794 struct optee_rtc_alarm *alarm) 795 { 796 struct optee_rtc_time *alarm_tm = NULL; 797 struct optee_rtc_time current_tm = { }; 798 TEE_Result res = TEE_ERROR_GENERIC; 799 vaddr_t rtc_base = get_base(); 800 uint32_t alrmar = io_read32(rtc_base + RTC_ALRMAR); 801 uint32_t cr = io_read32(rtc_base + RTC_CR); 802 uint32_t status = io_read32(rtc_base + RTC_SR); 803 804 alarm_tm = &alarm->time; 805 806 res = stm32_rtc_get_time(rtc, ¤t_tm); 807 if (res) 808 return res; 809 810 alarm_tm->tm_year = current_tm.tm_year; 811 alarm_tm->tm_mon = current_tm.tm_mon; 812 alarm_tm->tm_mday = ((alrmar & RTC_ALRMXR_DATE_UNITS_MASK) >> 813 RTC_ALRMXR_DATE_UNITS_SHIFT) + 814 ((alrmar & RTC_ALRMXR_DATE_TENS_MASK) >> 815 RTC_ALRMXR_DATE_TENS_SHIFT) * 10; 816 alarm_tm->tm_hour = ((alrmar & RTC_ALRMXR_HOUR_UNITS_MASK) >> 817 RTC_ALRMXR_HOUR_UNITS_SHIFT) + 818 ((alrmar & RTC_ALRMXR_HOUR_TENS_MASK) >> 819 RTC_ALRMXR_HOUR_TENS_SHIFT) * 10; 820 alarm_tm->tm_min = ((alrmar & RTC_ALRMXR_MIN_UNITS_MASK) >> 821 RTC_ALRMXR_MIN_UNITS_SHIFT) + 822 ((alrmar & RTC_ALRMXR_MIN_TENS_MASK) >> 823 RTC_ALRMXR_MIN_TENS_SHIFT) * 10; 824 alarm_tm->tm_sec = ((alrmar & RTC_ALRMXR_MIN_UNITS_MASK) >> 825 RTC_ALRMXR_MIN_UNITS_SHIFT) + 826 ((alrmar & RTC_ALRMXR_MIN_TENS_MASK) >> 827 RTC_ALRMXR_MIN_TENS_SHIFT) * 10; 828 829 if (rtc_timecmp(alarm_tm, ¤t_tm) < 0) { 830 if (current_tm.tm_mon == 11) { 831 alarm_tm->tm_mon = 0; 832 alarm_tm->tm_year += 1; 833 } else { 834 alarm_tm->tm_mon += 1; 835 } 836 } 837 838 alarm->enabled = cr & RTC_CR_ALRAE; 839 alarm->pending = status & RTC_SR_ALRAF; 840 841 return TEE_SUCCESS; 842 } 843 844 static TEE_Result stm32_rtc_enable_alarm(struct rtc *rtc __unused, bool enabled) 845 { 846 vaddr_t rtc_base = get_base(); 847 848 stm32_rtc_write_unprotect(); 849 850 if (enabled) 851 io_setbits32(rtc_base + RTC_CR, RTC_CR_ALRAIE | RTC_CR_ALRAE); 852 else 853 io_clrbits32(rtc_base + RTC_CR, RTC_CR_ALRAIE | RTC_CR_ALRAE); 854 855 stm32_rtc_clear_events(RTC_SCR_CALRAF); 856 857 stm32_rtc_write_protect(); 858 859 return TEE_SUCCESS; 860 } 861 862 static void stm32_rtc_add_one_month(struct optee_rtc_time *tm) 863 { 864 tm->tm_mon++; 865 if (tm->tm_mon > 11) { 866 tm->tm_mon = 0; 867 tm->tm_year++; 868 } 869 870 /* Saturate to the next month last day */ 871 tm->tm_mday = MIN(tm->tm_mday, 872 rtc_get_month_days(tm->tm_mon, tm->tm_year)); 873 } 874 875 static TEE_Result stm32_rtc_valid_alarm_time(struct rtc *rtc, 876 struct optee_rtc_time *tm) 877 { 878 struct optee_rtc_time current_tm = { }; 879 TEE_Result res = TEE_ERROR_GENERIC; 880 struct optee_rtc_time *max = NULL; 881 882 /* 883 * Assuming current date is M-D-Y H:M:S. 884 * RTC alarm can't be set on a specific month and year. 885 * So the valid alarm range is: 886 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S 887 */ 888 889 res = stm32_rtc_get_time(rtc, ¤t_tm); 890 if (res) 891 return res; 892 893 /* Don't allow alarm to be set in the past. */ 894 if (rtc_timecmp(¤t_tm, tm) >= 0) 895 return TEE_ERROR_BAD_PARAMETERS; 896 897 max = ¤t_tm; 898 899 stm32_rtc_add_one_month(max); 900 901 if (rtc_timecmp(max, tm) <= 0) 902 return TEE_ERROR_BAD_PARAMETERS; 903 904 return TEE_SUCCESS; 905 } 906 907 static TEE_Result stm32_rtc_set_alarm(struct rtc *rtc, 908 struct optee_rtc_alarm *alarm) 909 { 910 struct optee_rtc_time *alarm_time = &alarm->time; 911 TEE_Result res = TEE_ERROR_GENERIC; 912 vaddr_t rtc_base = get_base(); 913 uint32_t alrmar = 0; 914 uint32_t cr = io_read32(rtc_base + RTC_CR); 915 uint32_t prer = io_read32(rtc_base + RTC_PRER); 916 uint32_t prediv_s = prer & RTC_PRER_PREDIV_S_MASK; 917 918 /* tm_year and tm_mon are not used because not supported by RTC */ 919 alrmar |= ((alarm_time->tm_mday / 10) << RTC_ALRMXR_DATE_TENS_SHIFT) & 920 RTC_ALRMXR_DATE_TENS_MASK; 921 alrmar |= ((alarm_time->tm_mday % 10) << RTC_ALRMXR_DATE_UNITS_SHIFT) & 922 RTC_ALRMXR_DATE_UNITS_MASK; 923 /* 24-hour format */ 924 alrmar &= ~RTC_ALRMXR_PM; 925 alrmar |= ((alarm_time->tm_hour / 10) << RTC_ALRMXR_HOUR_TENS_SHIFT) & 926 RTC_ALRMXR_HOUR_TENS_MASK; 927 alrmar |= ((alarm_time->tm_hour % 10) << RTC_ALRMXR_HOUR_UNITS_SHIFT) & 928 RTC_ALRMXR_HOUR_UNITS_MASK; 929 alrmar |= ((alarm_time->tm_min / 10) << RTC_ALRMXR_MIN_TENS_SHIFT) & 930 RTC_ALRMXR_MIN_TENS_MASK; 931 alrmar |= ((alarm_time->tm_min % 10) << RTC_ALRMXR_MIN_UNITS_SHIFT) & 932 RTC_ALRMXR_MIN_UNITS_MASK; 933 alrmar |= ((alarm_time->tm_sec / 10) << RTC_ALRMXR_SEC_TENS_SHIFT) & 934 RTC_ALRMXR_SEC_TENS_MASK; 935 alrmar |= ((alarm_time->tm_sec % 10) << RTC_ALRMXR_SEC_UNITS_SHIFT) & 936 RTC_ALRMXR_SEC_UNITS_MASK; 937 938 if ((alrmar & !RTC_ALRMXR_SEC_MASK) && prediv_s < 3) { 939 EMSG("RTC Alarm conditions not met"); 940 return TEE_ERROR_BAD_STATE; 941 } 942 943 stm32_rtc_write_unprotect(); 944 945 res = stm32_rtc_valid_alarm_time(rtc, alarm_time); 946 if (res) { 947 stm32_rtc_write_unprotect(); 948 return res; 949 } 950 951 /* Disable Alarm */ 952 cr &= ~RTC_CR_ALRAE; 953 io_write32(rtc_base + RTC_CR, cr); 954 955 io_write32(rtc_base + RTC_ALRMAR, alrmar); 956 957 stm32_rtc_enable_alarm(rtc, alarm->enabled); 958 959 stm32_rtc_write_protect(); 960 961 return TEE_SUCCESS; 962 } 963 964 static TEE_Result stm32_rtc_cancel_wait_alarm(struct rtc *rtc __unused) 965 { 966 rtc_dev.wait_alarm_return_status = RTC_WAIT_ALARM_CANCELED; 967 notif_send_async(rtc_dev.notif_id, 0); 968 969 return TEE_SUCCESS; 970 } 971 972 static TEE_Result 973 stm32_rtc_wait_alarm(struct rtc *rtc __unused, 974 enum rtc_wait_alarm_status *return_status) 975 { 976 TEE_Result res = TEE_ERROR_GENERIC; 977 978 rtc_dev.wait_alarm_return_status = RTC_WAIT_ALARM_RESET; 979 980 /* Wait until a notification arrives - blocking */ 981 res = notif_wait(rtc_dev.notif_id); 982 if (res) 983 return res; 984 985 if (rtc_dev.wait_alarm_return_status == 986 RTC_WAIT_ALARM_CANCELED) { 987 *return_status = RTC_WAIT_ALARM_CANCELED; 988 stm32_rtc_enable_alarm(rtc, 0); 989 } else { 990 *return_status = RTC_WAIT_ALARM_ALARM_OCCURRED; 991 } 992 993 return TEE_SUCCESS; 994 } 995 996 static const struct rtc_ops stm32_rtc_ops = { 997 .get_time = stm32_rtc_get_time, 998 .set_time = stm32_rtc_set_time, 999 .read_alarm = stm32_rtc_read_alarm, 1000 .set_alarm = stm32_rtc_set_alarm, 1001 .enable_alarm = stm32_rtc_enable_alarm, 1002 .wait_alarm = stm32_rtc_wait_alarm, 1003 .cancel_wait = stm32_rtc_cancel_wait_alarm, 1004 }; 1005 1006 static struct rtc stm32_rtc = { 1007 .ops = &stm32_rtc_ops, 1008 .range_min = RTC_TIME(YEAR_REF, 0, 1, 0, 0, 0, 0, 0), 1009 .range_max = RTC_TIME(YEAR_MAX, 11, 31, 4, 23, 59, 59, 999), 1010 }; 1011 1012 static TEE_Result stm32_rtc_probe(const void *fdt, int node, 1013 const void *compat_data) 1014 { 1015 TEE_Result res = TEE_ERROR_GENERIC; 1016 bool is_tdcid = false; 1017 1018 rtc_dev.compat = compat_data; 1019 1020 if (rtc_dev.compat->has_rif_support) { 1021 res = stm32_rifsc_check_tdcid(&is_tdcid); 1022 if (res) 1023 return res; 1024 } 1025 1026 res = parse_dt(fdt, node); 1027 if (res) { 1028 memset(&rtc_dev, 0, sizeof(rtc_dev)); 1029 return res; 1030 } 1031 1032 /* Unbalanced clock enable to ensure RTC core clock is always on */ 1033 res = clk_enable(rtc_dev.rtc_ck); 1034 if (res) 1035 panic("Couldn't enable RTC clock"); 1036 1037 if (clk_get_rate(rtc_dev.pclk) < (clk_get_rate(rtc_dev.rtc_ck) * 7)) 1038 rtc_dev.flags |= RTC_FLAGS_READ_TWICE; 1039 1040 if (rtc_dev.compat->has_rif_support) { 1041 res = clk_enable(rtc_dev.pclk); 1042 if (res) 1043 panic("Could not enable RTC bus clock"); 1044 1045 apply_rif_config(is_tdcid); 1046 1047 /* 1048 * Verify if applied RIF config will not disable 1049 * other functionalities of this driver. 1050 */ 1051 res = check_rif_config(); 1052 if (res) 1053 panic("Incompatible RTC RIF configuration"); 1054 1055 clk_disable(rtc_dev.pclk); 1056 } 1057 1058 res = stm32_rtc_init(); 1059 if (res) 1060 return res; 1061 1062 rtc_register(&stm32_rtc); 1063 1064 if (IS_ENABLED(CFG_RTC_PTA) && IS_ENABLED(CFG_CORE_ASYNC_NOTIF) && 1065 rtc_dev.is_secured) { 1066 res = notif_alloc_async_value(&rtc_dev.notif_id); 1067 if (res) 1068 return res; 1069 1070 /* Unbalanced clock enable to ensure IRQ interface is alive */ 1071 res = clk_enable(rtc_dev.pclk); 1072 if (res) 1073 goto out_rtc_secured; 1074 1075 interrupt_enable(rtc_dev.itr_chip, rtc_dev.itr_num); 1076 1077 return TEE_SUCCESS; 1078 1079 out_rtc_secured: 1080 notif_free_async_value(rtc_dev.notif_id); 1081 return res; 1082 } 1083 1084 return TEE_SUCCESS; 1085 } 1086 1087 static const struct rtc_compat mp25_compat = { 1088 .has_seccfgr = true, 1089 .has_rif_support = true, 1090 }; 1091 1092 static const struct rtc_compat mp15_compat = { 1093 .has_seccfgr = false, 1094 .has_rif_support = false, 1095 }; 1096 1097 static const struct rtc_compat mp13_compat = { 1098 .has_seccfgr = true, 1099 .has_rif_support = false, 1100 }; 1101 1102 static const struct dt_device_match stm32_rtc_match_table[] = { 1103 { 1104 .compatible = "st,stm32mp25-rtc", 1105 .compat_data = &mp25_compat, 1106 }, 1107 { 1108 .compatible = "st,stm32mp1-rtc", 1109 .compat_data = &mp15_compat, 1110 }, 1111 { 1112 .compatible = "st,stm32mp13-rtc", 1113 .compat_data = &mp13_compat, 1114 }, 1115 { } 1116 }; 1117 1118 DEFINE_DT_DRIVER(stm32_rtc_dt_driver) = { 1119 .name = "stm32-rtc", 1120 .match_table = stm32_rtc_match_table, 1121 .probe = stm32_rtc_probe, 1122 }; 1123