core: riscv: Add TLB operation related to virtual address and ASID

Add TLB invalidate function which is corresponding to virtual address
and ASID. The commit also adds missing declaration of tlbi_va

core: riscv: Add TLB operation related to virtual address and ASID

Add TLB invalidate function which is corresponding to virtual address
and ASID. The commit also adds missing declaration of tlbi_va_allasid().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: fix race in mobj_reg_shm_dec_map()

Fixes a race in mobj_reg_shm_dec_map() when r->mm is NULL. This is
similar to the race fixed by commit 06ea466f9c19 ("core: fix race in
mobj_reg_shm_inc_map(

core: fix race in mobj_reg_shm_dec_map()

Fixes a race in mobj_reg_shm_dec_map() when r->mm is NULL. This is
similar to the race fixed by commit 06ea466f9c19 ("core: fix race in
mobj_reg_shm_inc_map()"), but with one more possibility.

The problem goes like:
A. Thread 1 calls mobj_reg_shm_dec_map() at the same time as thread 2
calls mobj_reg_shm_inc_map().
B. Thread 1 decreases mapcount to zero and tries to take the spinlock,
but thread 1 is suspended before it has acquired the spinlock.
C. Thread 2 sees that mapcount is zero and takes the spinlock and maps
the memory.
D. Thread 2 calls mobj_reg_shm_dec_map(), mapcount reaches zero again
and the shared memory is unmapped and r->mm is set to NULL.
E. Thread 1 is finally resumed and acquires the spinlock, mapcount is still
zero but r->mm is also NULL.

To fix the problem at step E above check that r->mm is still non-NULL.

Note that the same fix isn't needed for ffa_dec_map() since
unmap_helper() checks that mf->mm is non-NULL first.

Fixes: 06ea466f9c19 ("core: fix race in mobj_reg_shm_inc_map()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Olivier Masse <olivier.masse@nxp.com>

show more ...

core: riscv: Add cflags for excluding source files from ftrace

Some C source files may lead to incorrect behaviors in ftrace. Exclude
them when the system is compiled with ftrace support.

Signed-of

core: riscv: Add cflags for excluding source files from ftrace

Some C source files may lead to incorrect behaviors in ftrace. Exclude
them when the system is compiled with ftrace support.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: riscv: Implement timer related functions for ftrace support

Implement barrier_read_counter_timer() to read the timer value after a
barrier. Implement read_cntfrq() to get the frequency of mach

core: riscv: Implement timer related functions for ftrace support

Implement barrier_read_counter_timer() to read the timer value after a
barrier. Implement read_cntfrq() to get the frequency of machine timer
counter. The read_time() is moved from header to C source file to reduce
the code size.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

libutils: Add riscv.S to make it available for core and TA libs

Some assembly macros are necessary for both OP-TEE core and TA
libraries. Therefore, we add riscv specific assembly file into libutils

libutils: Add riscv.S to make it available for core and TA libs

Some assembly macros are necessary for both OP-TEE core and TA
libraries. Therefore, we add riscv specific assembly file into libutils
and move some assembly related macros from riscv.h to riscv.S.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: spmc: handle missing FFA_MSG_SEND_VM_DESTROYED

Handles the previously missing FFA_MSG_SEND_VM_DESTROYED message used to
signal the destruction of a non-secure guest. This is the counter part
o

core: spmc: handle missing FFA_MSG_SEND_VM_DESTROYED

Handles the previously missing FFA_MSG_SEND_VM_DESTROYED message used to
signal the destruction of a non-secure guest. This is the counter part
of FFA_MSG_SEND_VM_CREATED that is used to signal the creation of a
non-secure guest.

Fixes: a65dd3a6b64d ("core: spmc: support virtualization with SPMC at S-EL1")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-k3: main: Print the provisioned key information

During provisioning these values are fused using the signing
certificate.

The maximum value of Key Count is 2 (when BMPK is used).

Signed-off-b

plat-k3: main: Print the provisioned key information

During provisioning these values are fused using the signing
certificate.

The maximum value of Key Count is 2 (when BMPK is used).

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-k3: drivers: add TISCI call to retrieve the Keycnt and Keyrev

Add TISCI call to retrieve the key count and key revision fused during
provisioning.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@fou

plat-k3: drivers: add TISCI call to retrieve the Keycnt and Keyrev

Add TISCI call to retrieve the key count and key revision fused during
provisioning.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-k3: main: coding standard consistency

The coding standard requires a line between function definitions.

Add such a line to make it visually consistent with the recently added
secure_boot_infor

plat-k3: main: coding standard consistency

The coding standard requires a line between function definitions.

Add such a line to make it visually consistent with the recently added
secure_boot_information(void).

This commit also removes a duplicated include directive.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-k3: main: Print the revision of the Secure Board Configuration

If the board is booting with hardware authentication, print the software
revision.

The Software Revision is the value written to

plat-k3: main: Print the revision of the Secure Board Configuration

If the board is booting with hardware authentication, print the software
revision.

The Software Revision is the value written to the OTP eFuse during board
provisioning and it is only available in HS boards.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-k3: drivers: add TISCI call to retrieve the SWREV

This call is only available to OTP_REV_ID_SEC_BRDCFG

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerom

plat-k3: drivers: add TISCI call to retrieve the SWREV

This call is only available to OTP_REV_ID_SEC_BRDCFG

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-k3: drivers: add OTP revision read/write message descriptions

Add the TISCI message identifiers required for reading and writing
Software Revision and Key Revision to/from eFuses.

Signed-off-b

plat-k3: drivers: add OTP revision read/write message descriptions

Add the TISCI message identifiers required for reading and writing
Software Revision and Key Revision to/from eFuses.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: spmc: implement FFA_CONSOLE_LOG

Add FFA_CONSOLE_LOG interface support for enabling debug messages from
SPs as defined in FF-A v1.2. The message string is packed into the
registers of the call

core: spmc: implement FFA_CONSOLE_LOG

Add FFA_CONSOLE_LOG interface support for enabling debug messages from
SPs as defined in FF-A v1.2. The message string is packed into the
registers of the call so it doesn't require the existence of a shared
memory between the SPMC and the SPs. This makes it ideal for early debug
messages, however the length of the message is limited.
The received messages are forwarded to OP-TEE's trace output.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: thread: Add support for canary value randomization

Currently hardcoded magic number is used as thread stack canary,
an attacker with full control over the overflow can embed the
hardcoded cana

core: thread: Add support for canary value randomization

Currently hardcoded magic number is used as thread stack canary,
an attacker with full control over the overflow can embed the
hardcoded canary value on the right location to bypass the overflow
detection.

To add extra layer of security, redefine the canary value as variable,
such that the canary can be initialized during runtime.

The canaries are initialized with static values from thread_init_canaries()
during the early boot stage. The plat_get_random_stack_canaries() is
refactored to support arbitrary-length random numbers, and a new function
called thread_update_canaries() is created to fetch the random values and
update the thread canaries. For CFG_NS_VIRTUALIZATION=y, the updated
function is disabled.

Signed-off-by: Vincent Chuang <Vincent.Chuang@mediatek.com>
Signed-off-by: Randy Hsu <Randy-CY.Hsu@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: riscv: Use standard ABI Mnemonic for frame pointer

Some older toolchain might not recognize "fp". To fix it, we use
standard ABI Mnemonic "s0" instead of "fp".

Signed-off-by: Alvin Chang <alv

core: riscv: Use standard ABI Mnemonic for frame pointer

Some older toolchain might not recognize "fp". To fix it, we use
standard ABI Mnemonic "s0" instead of "fp".

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: riscv: Update saving panic registers from _utee_panic()

The _utee_panic() function only saves ra and s0(fp) onto stack. So we
only get them from the stack and save them as epc and s0 as abort

core: riscv: Update saving panic registers from _utee_panic()

The _utee_panic() function only saves ra and s0(fp) onto stack. So we
only get them from the stack and save them as epc and s0 as abort
registers.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: riscv: Add TA compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enable

core: riscv: Add TA compiler flags for stack unwinding

When the CFG_UNWIND is enabled, the frame pointer should not be omitted
by compiler. Add "-fno-omit-frame-pointer" compiler flag when we enable
the CFG_UNWIND to let compiler not to omit the frame pointer when it
builds TA.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

drivers: stm32_bsec: fix timeouts initialization

If OP-TEE is rescheduled right after the timeouts are initialized in
power_down_safmem() and power_up_safmem(), the timeout might be elapsed
when res

drivers: stm32_bsec: fix timeouts initialization

If OP-TEE is rescheduled right after the timeouts are initialized in
power_down_safmem() and power_up_safmem(), the timeout might be elapsed
when resuming the function. This would cause the while loop to break
instantly and there will be no delay between configuring the registers
and reading the status.

Initializes the timeout after configuring the registers.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-stm32mp1: restore SYSRAM for SCMI message on STM32MP13

Restores use of SYSRAM last page for STM32MP13 for SCMI communication
as U-Boot and Linux kernel device trees are not yet updated to use O

plat-stm32mp1: restore SYSRAM for SCMI message on STM32MP13

Restores use of SYSRAM last page for STM32MP13 for SCMI communication
as U-Boot and Linux kernel device trees are not yet updated to use OP-TEE
native shared memory instead.

Fixes: 89ba3422ee80 ("plat-stm32mp1: scmi_server: default use OP-TEE shared memory")
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32mp13: update stm32mp13 SoC and board DTS files

Updates STM32MP13* SoC DTSI files and STM32MP135F-DK board DTS file
and related DT binding header files.

Acked-by: Gatien Chevallier <gatien

dts: stm32mp13: update stm32mp13 SoC and board DTS files

Updates STM32MP13* SoC DTSI files and STM32MP135F-DK board DTS file
and related DT binding header files.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_i2c: fix pin secure configuration for STM32MP13

Fixes the implementation for configuring I2C pins as secure
for STM32MP13. The implementation must consider the number of pins
in the r

drivers: stm32_i2c: fix pin secure configuration for STM32MP13

Fixes the implementation for configuring I2C pins as secure
for STM32MP13. The implementation must consider the number of pins
in the related pinctrl instance.

Fixes: 1c81e5f9458a ("drivers: stm32_gpio: temporary GPIO configuration for STM32MP13")
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_etzpc: register to dt_driver as simple bus

Registers stm32_etzpc driver to dt_drver as simple bus as expected
by forth coming update of STM32MP13 SoC variant DTSI files.

Removes stm3

drivers: stm32_etzpc: register to dt_driver as simple bus

Registers stm32_etzpc driver to dt_drver as simple bus as expected
by forth coming update of STM32MP13 SoC variant DTSI files.

Removes stm32_etzpc_init() that is not used by the platform.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_rstctrl: add STM32MP13 compatible

Updates stm32_rstctrl driver for STM32MP13 variant support.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carri

drivers: stm32_rstctrl: add STM32MP13 compatible

Updates stm32_rstctrl driver for STM32MP13 variant support.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-stm32mp1: allow use of SRAMs as TZSRAM

Allows CFG_TZSRAM_BASE/_SIZE to cover SRAM1, SRAM2, SRAM3 and SRAM4
to enlarge pager page pool and enhance pager performances. When so,
the SRAMs which TZ

plat-stm32mp1: allow use of SRAMs as TZSRAM

Allows CFG_TZSRAM_BASE/_SIZE to cover SRAM1, SRAM2, SRAM3 and SRAM4
to enlarge pager page pool and enhance pager performances. When so,
the SRAMs which TZSRAM lie in are registered as secure.

Using these internal memory requires SCMI communication to not use
SYSRAM last page for example by using OP-TEE native shared memory instead.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-stm32mp1: shared_resources: consider SRAMs

Adds SRAMs to the STM32MP15 shared resources.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.ca

plat-stm32mp1: shared_resources: consider SRAMs

Adds SRAMs to the STM32MP15 shared resources.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...