1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <drivers/gpio.h> 12 #include <drivers/pinctrl.h> 13 #include <drivers/stm32_gpio.h> 14 #include <io.h> 15 #include <kernel/dt.h> 16 #include <kernel/boot.h> 17 #include <kernel/panic.h> 18 #include <kernel/spinlock.h> 19 #include <libfdt.h> 20 #include <mm/core_memprot.h> 21 #include <stdbool.h> 22 #include <stm32_util.h> 23 #include <sys/queue.h> 24 #include <trace.h> 25 #include <util.h> 26 27 #ifndef CFG_DRIVERS_GPIO 28 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 29 #endif 30 31 #define GPIO_PIN_MAX 15 32 33 #define GPIO_MODER_OFFSET 0x00 34 #define GPIO_OTYPER_OFFSET 0x04 35 #define GPIO_OSPEEDR_OFFSET 0x08 36 #define GPIO_PUPDR_OFFSET 0x0c 37 #define GPIO_IDR_OFFSET 0x10 38 #define GPIO_ODR_OFFSET 0x14 39 #define GPIO_BSRR_OFFSET 0x18 40 #define GPIO_AFRL_OFFSET 0x20 41 #define GPIO_AFRH_OFFSET 0x24 42 #define GPIO_SECR_OFFSET 0x30 43 44 #define GPIO_ALT_LOWER_LIMIT 0x8 45 46 #define GPIO_MODE_MASK GENMASK_32(1, 0) 47 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 48 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 49 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 50 51 #define DT_GPIO_BANK_SHIFT 12 52 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 53 #define DT_GPIO_PIN_SHIFT 8 54 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 55 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 56 57 #define DT_GPIO_BANK_NAME0 "GPIOA" 58 59 /* 60 * struct stm32_pinctrl_array - Array of pins in a pin control state 61 * @count: Number of cells in @pinctrl 62 * @pinctrl: Pin control configuration 63 */ 64 struct stm32_pinctrl_array { 65 size_t count; 66 struct stm32_pinctrl pinctrl[]; 67 }; 68 69 /** 70 * struct stm32_gpio_bank - GPIO bank instance 71 * 72 * @base: base address of the GPIO controller registers. 73 * @clock: clock identifier. 74 * @gpio_chip: GPIO chip reference for that GPIO bank 75 * @ngpios: number of GPIOs. 76 * @bank_id: Id of the bank. 77 * @lock: lock protecting the GPIO bank access. 78 * @sec_support: True if bank supports pin security protection, otherwise false 79 * @seccfgr: Secure configuration register value. 80 * @link: Link in bank list 81 */ 82 struct stm32_gpio_bank { 83 vaddr_t base; 84 struct clk *clock; 85 struct gpio_chip gpio_chip; 86 unsigned int ngpios; 87 unsigned int bank_id; 88 unsigned int lock; 89 STAILQ_ENTRY(stm32_gpio_bank) link; 90 }; 91 92 static unsigned int gpio_lock; 93 94 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 95 STAILQ_HEAD_INITIALIZER(bank_list); 96 97 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 98 99 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 100 { 101 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 102 } 103 104 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 105 unsigned int gpio_pin) 106 { 107 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 108 enum gpio_level level = GPIO_LEVEL_HIGH; 109 unsigned int reg_offset = 0; 110 unsigned int mode = 0; 111 112 assert(gpio_pin < bank->ngpios); 113 114 if (clk_enable(bank->clock)) 115 panic(); 116 117 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 118 GPIO_MODE_MASK; 119 120 switch (mode) { 121 case GPIO_MODE_INPUT: 122 reg_offset = GPIO_IDR_OFFSET; 123 break; 124 case GPIO_MODE_OUTPUT: 125 reg_offset = GPIO_ODR_OFFSET; 126 break; 127 default: 128 panic(); 129 } 130 131 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 132 level = GPIO_LEVEL_HIGH; 133 else 134 level = GPIO_LEVEL_LOW; 135 136 clk_disable(bank->clock); 137 138 return level; 139 } 140 141 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 142 enum gpio_level level) 143 { 144 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 145 146 assert(gpio_pin < bank->ngpios); 147 148 if (clk_enable(bank->clock)) 149 panic(); 150 151 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 152 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 153 154 if (level == GPIO_LEVEL_HIGH) 155 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 156 else 157 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 158 159 clk_disable(bank->clock); 160 } 161 162 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 163 unsigned int gpio_pin) 164 { 165 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 166 uint32_t mode = 0; 167 168 assert(gpio_pin < bank->ngpios); 169 170 if (clk_enable(bank->clock)) 171 panic(); 172 173 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 174 GPIO_MODE_MASK; 175 176 clk_disable(bank->clock); 177 178 switch (mode) { 179 case GPIO_MODE_INPUT: 180 return GPIO_DIR_IN; 181 case GPIO_MODE_OUTPUT: 182 return GPIO_DIR_OUT; 183 default: 184 panic(); 185 } 186 } 187 188 static void stm32_gpio_set_direction(struct gpio_chip *chip, 189 unsigned int gpio_pin, 190 enum gpio_dir direction) 191 { 192 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 193 uint32_t exceptions = 0; 194 uint32_t mode = 0; 195 196 assert(gpio_pin < bank->ngpios); 197 198 if (direction == GPIO_DIR_IN) 199 mode = GPIO_MODE_INPUT; 200 else 201 mode = GPIO_MODE_OUTPUT; 202 203 if (clk_enable(bank->clock)) 204 panic(); 205 exceptions = cpu_spin_lock_xsave(&gpio_lock); 206 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 207 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 208 SHIFT_U32(mode, gpio_pin << 1)); 209 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 210 clk_disable(bank->clock); 211 } 212 213 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 214 struct gpio *gpio) 215 { 216 assert(is_stm32_gpio_chip(chip)); 217 free(gpio); 218 } 219 220 static const struct gpio_ops stm32_gpio_ops = { 221 .get_direction = stm32_gpio_get_direction, 222 .set_direction = stm32_gpio_set_direction, 223 .get_value = stm32_gpio_get_level, 224 .set_value = stm32_gpio_set_level, 225 .put = stm32_gpio_put_gpio, 226 }; 227 228 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 229 { 230 return chip && chip->ops == &stm32_gpio_ops; 231 } 232 233 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 234 { 235 struct stm32_gpio_bank *bank = NULL; 236 237 STAILQ_FOREACH(bank, &bank_list, link) 238 if (bank_id == bank->bank_id) 239 return bank; 240 241 panic(); 242 } 243 244 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 245 static void __maybe_unused get_gpio_cfg(uint32_t bank_id, uint32_t pin, 246 struct gpio_cfg *cfg) 247 { 248 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 249 250 if (clk_enable(bank->clock)) 251 panic(); 252 253 /* 254 * Save GPIO configuration bits spread over the few bank registers. 255 * 1bit fields are accessed at bit position being the pin index. 256 * 2bit fields are accessed at bit position being twice the pin index. 257 * 4bit fields are accessed at bit position being fourth the pin index 258 * but accessed from 2 32bit registers at incremental addresses. 259 */ 260 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 261 GPIO_MODE_MASK; 262 263 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 264 265 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 266 (pin << 1)) & GPIO_OSPEED_MASK; 267 268 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 269 GPIO_PUPD_PULL_MASK; 270 271 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 272 273 if (pin < GPIO_ALT_LOWER_LIMIT) 274 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 275 (pin << 2)) & GPIO_ALTERNATE_MASK; 276 else 277 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 278 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 279 GPIO_ALTERNATE_MASK; 280 281 clk_disable(bank->clock); 282 } 283 284 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 285 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 286 { 287 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 288 uint32_t exceptions = 0; 289 290 if (clk_enable(bank->clock)) 291 panic(); 292 exceptions = cpu_spin_lock_xsave(&gpio_lock); 293 294 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 295 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 296 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 297 SHIFT_U32(cfg->mode, pin << 1)); 298 299 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 300 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 301 SHIFT_U32(cfg->otype, pin)); 302 303 /* Load GPIO Output Speed confguration, 2bit value */ 304 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 305 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 306 SHIFT_U32(cfg->ospeed, pin << 1)); 307 308 /* Load GPIO pull configuration, 2bit value */ 309 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 310 SHIFT_U32(cfg->pupd, pin << 1)); 311 312 /* Load pin mux Alternate Function configuration, 4bit value */ 313 if (pin < GPIO_ALT_LOWER_LIMIT) { 314 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 315 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 316 SHIFT_U32(cfg->af, pin << 2)); 317 } else { 318 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 319 320 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 321 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 322 SHIFT_U32(cfg->af, shift)); 323 } 324 325 /* Load GPIO Output direction confuguration, 1bit */ 326 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 327 328 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 329 clk_disable(bank->clock); 330 } 331 332 #if !defined(CFG_DRIVERS_PINCTRL) 333 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 334 { 335 size_t n = 0; 336 337 for (n = 0; n < cnt; n++) 338 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 339 &pinctrl[n].active_cfg); 340 } 341 342 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 343 { 344 size_t n = 0; 345 346 for (n = 0; n < cnt; n++) 347 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 348 &pinctrl[n].standby_cfg); 349 } 350 351 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 352 { 353 size_t n = 0; 354 355 for (n = 0; n < cnt; n++) 356 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 357 &pinctrl[n].standby_cfg); 358 } 359 360 /* Panic if GPIO bank information from platform do not match DTB description */ 361 static void ckeck_gpio_bank(const void *fdt, uint32_t bank, int pinctrl_node) 362 { 363 int pinctrl_subnode = 0; 364 365 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 366 const fdt32_t *cuint = NULL; 367 368 if (fdt_getprop(fdt, pinctrl_subnode, 369 "gpio-controller", NULL) == NULL) 370 continue; 371 372 /* Check bank register offset matches platform assumptions */ 373 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 374 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 375 continue; 376 377 /* Check controller is enabled */ 378 if (fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED) 379 panic(); 380 381 return; 382 } 383 384 panic(); 385 } 386 #endif /*CFG_DRIVERS_PINCTRL*/ 387 388 /* Count pins described in the DT node and get related data if possible */ 389 static int get_pinctrl_from_fdt(const void *fdt, int node, 390 struct stm32_pinctrl *pinctrl, size_t count) 391 { 392 const fdt32_t *cuint = NULL; 393 const fdt32_t *slewrate = NULL; 394 int len = 0; 395 int __maybe_unused pinctrl_node = 0; 396 uint32_t i = 0; 397 uint32_t speed = GPIO_OSPEED_LOW; 398 uint32_t pull = GPIO_PUPD_NO_PULL; 399 size_t found = 0; 400 401 cuint = fdt_getprop(fdt, node, "pinmux", &len); 402 if (!cuint) 403 return -FDT_ERR_NOTFOUND; 404 405 #if !defined(CFG_DRIVERS_PINCTRL) 406 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 407 if (pinctrl_node < 0) 408 return -FDT_ERR_NOTFOUND; 409 #endif 410 411 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 412 if (slewrate) 413 speed = fdt32_to_cpu(*slewrate); 414 415 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 416 pull = GPIO_PUPD_PULL_UP; 417 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 418 pull = GPIO_PUPD_PULL_DOWN; 419 420 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 421 uint32_t pincfg = 0; 422 uint32_t bank = 0; 423 uint32_t pin = 0; 424 uint32_t mode = 0; 425 uint32_t alternate = 0; 426 uint32_t odata = 0; 427 bool opendrain = false; 428 429 pincfg = fdt32_to_cpu(*cuint); 430 cuint++; 431 432 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 433 434 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 435 436 mode = pincfg & DT_GPIO_MODE_MASK; 437 438 switch (mode) { 439 case 0: 440 mode = GPIO_MODE_INPUT; 441 break; 442 case 1: 443 case 2: 444 case 3: 445 case 4: 446 case 5: 447 case 6: 448 case 7: 449 case 8: 450 case 9: 451 case 10: 452 case 11: 453 case 12: 454 case 13: 455 case 14: 456 case 15: 457 case 16: 458 alternate = mode - 1U; 459 mode = GPIO_MODE_ALTERNATE; 460 break; 461 case 17: 462 mode = GPIO_MODE_ANALOG; 463 break; 464 default: 465 mode = GPIO_MODE_OUTPUT; 466 break; 467 } 468 469 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 470 opendrain = true; 471 472 if (fdt_getprop(fdt, node, "output-high", NULL) && 473 mode == GPIO_MODE_INPUT) { 474 mode = GPIO_MODE_OUTPUT; 475 odata = 1; 476 } 477 478 if (fdt_getprop(fdt, node, "output-low", NULL) && 479 mode == GPIO_MODE_INPUT) { 480 mode = GPIO_MODE_OUTPUT; 481 odata = 0; 482 } 483 484 #if !defined(CFG_DRIVERS_PINCTRL) 485 /* Check GPIO bank clock/base address against platform */ 486 ckeck_gpio_bank(fdt, bank, pinctrl_node); 487 #endif 488 489 if (found < count) { 490 struct stm32_pinctrl *ref = &pinctrl[found]; 491 492 ref->bank = (uint8_t)bank; 493 ref->pin = (uint8_t)pin; 494 #ifdef CFG_DRIVERS_PINCTRL 495 ref->cfg.mode = mode; 496 if (opendrain) 497 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 498 else 499 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 500 ref->cfg.ospeed = speed; 501 ref->cfg.pupd = pull; 502 ref->cfg.od = odata; 503 ref->cfg.af = alternate; 504 #else 505 ref->active_cfg.mode = mode; 506 ref->active_cfg.otype = opendrain ? 1 : 0; 507 ref->active_cfg.ospeed = speed; 508 ref->active_cfg.pupd = pull; 509 ref->active_cfg.od = odata; 510 ref->active_cfg.af = alternate; 511 /* Default to analog mode for standby state */ 512 ref->standby_cfg.mode = GPIO_MODE_ANALOG; 513 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL; 514 #endif 515 } 516 517 found++; 518 } 519 520 return (int)found; 521 } 522 523 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 524 struct gpio **out_gpio) 525 { 526 TEE_Result res = TEE_ERROR_GENERIC; 527 struct stm32_gpio_bank *bank = data; 528 struct gpio *gpio = NULL; 529 unsigned int shift_1b = 0; 530 unsigned int shift_2b = 0; 531 uint32_t exceptions = 0; 532 uint32_t otype = 0; 533 uint32_t pupd = 0; 534 uint32_t mode = 0; 535 536 res = gpio_dt_alloc_pin(pargs, &gpio); 537 if (res) 538 return res; 539 540 if (gpio->pin >= bank->ngpios) { 541 DMSG("Invalid GPIO reference"); 542 free(gpio); 543 return TEE_ERROR_GENERIC; 544 } 545 546 shift_1b = gpio->pin; 547 shift_2b = SHIFT_U32(gpio->pin, 1); 548 549 if (gpio->dt_flags & GPIO_PULL_UP) 550 pupd = GPIO_PUPD_PULL_UP; 551 else if (gpio->dt_flags & GPIO_PULL_DOWN) 552 pupd = GPIO_PUPD_PULL_DOWN; 553 else 554 pupd = GPIO_PUPD_NO_PULL; 555 556 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 557 otype = GPIO_OTYPE_OPEN_DRAIN; 558 else 559 otype = GPIO_OTYPE_PUSH_PULL; 560 561 if (clk_enable(bank->clock)) 562 panic(); 563 exceptions = cpu_spin_lock_xsave(&gpio_lock); 564 565 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 566 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 567 SHIFT_U32(mode, shift_2b)); 568 569 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 570 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 571 SHIFT_U32(otype, shift_1b)); 572 573 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 574 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 575 SHIFT_U32(pupd, shift_2b)); 576 577 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 578 clk_disable(bank->clock); 579 580 gpio->chip = &bank->gpio_chip; 581 582 *out_gpio = gpio; 583 584 return TEE_SUCCESS; 585 } 586 587 /* Get bank ID from bank node property st,bank-name or panic on failure */ 588 static unsigned int dt_get_bank_id(const void *fdt, int node) 589 { 590 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 591 const fdt32_t *cuint = NULL; 592 int len = 0; 593 594 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 595 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 596 if (!cuint || (len != dt_name_len + 1)) 597 panic("Missing/wrong st,bank-name property"); 598 599 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 600 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 601 panic("Wrong st,bank-name property"); 602 603 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 604 } 605 606 /* 607 * Return whether or not the GPIO bank related to a DT node is already 608 * registered in the GPIO bank link. 609 */ 610 static bool bank_is_registered(const void *fdt, int node) 611 { 612 unsigned int bank_id = dt_get_bank_id(fdt, node); 613 struct stm32_gpio_bank *bank = NULL; 614 615 STAILQ_FOREACH(bank, &bank_list, link) 616 if (bank->bank_id == bank_id) 617 return true; 618 619 return false; 620 } 621 622 /* Get GPIO bank information from the DT */ 623 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 624 const void *compat_data __unused, 625 int range_offset, 626 struct stm32_gpio_bank **out_bank) 627 { 628 TEE_Result res = TEE_ERROR_GENERIC; 629 struct stm32_gpio_bank *bank = NULL; 630 const fdt32_t *cuint = NULL; 631 struct io_pa_va pa_va = { }; 632 struct clk *clk = NULL; 633 size_t blen = 0; 634 paddr_t pa = 0; 635 int len = 0; 636 int i = 0; 637 638 assert(out_bank); 639 640 /* Probe deferrable devices first */ 641 res = clk_dt_get_by_index(fdt, node, 0, &clk); 642 if (res) 643 return res; 644 645 bank = calloc(1, sizeof(*bank)); 646 if (!bank) 647 return TEE_ERROR_OUT_OF_MEMORY; 648 649 /* 650 * Do not rely *only* on the "reg" property to get the address, 651 * but consider also the "ranges" translation property 652 */ 653 pa = fdt_reg_base_address(fdt, node); 654 if (pa == DT_INFO_INVALID_REG) 655 panic("missing reg property"); 656 657 pa_va.pa = pa + range_offset; 658 659 blen = fdt_reg_size(fdt, node); 660 if (blen == DT_INFO_INVALID_REG_SIZE) 661 panic("missing reg size property"); 662 663 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 664 bank->base = io_pa_or_va_secure(&pa_va, blen); 665 bank->bank_id = dt_get_bank_id(fdt, node); 666 bank->clock = clk; 667 bank->gpio_chip.ops = &stm32_gpio_ops; 668 669 /* Parse gpio-ranges with its 4 parameters */ 670 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 671 len /= sizeof(*cuint); 672 if (len % 4) 673 panic("wrong gpio-ranges syntax"); 674 675 /* Get the last defined gpio line (offset + nb of pins) */ 676 for (i = 0; i < len / 4; i++) { 677 bank->ngpios = MAX(bank->ngpios, 678 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 679 fdt32_to_cpu(*(cuint + 3)))); 680 cuint += 4; 681 } 682 683 *out_bank = bank; 684 return TEE_SUCCESS; 685 } 686 687 static void set_bank_gpio_non_secure(struct stm32_gpio_bank *bank) 688 { 689 unsigned int pin = 0; 690 691 for (pin = 0; pin <= bank->ngpios; pin++) 692 stm32_gpio_set_secure_cfg(bank->bank_id, pin, false); 693 } 694 695 /* Parse a pinctrl node to register the GPIO banks it describes */ 696 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 697 const void *compat_data) 698 { 699 TEE_Result res = TEE_SUCCESS; 700 const fdt32_t *cuint = NULL; 701 int range_offs = 0; 702 int b_node = 0; 703 int len = 0; 704 705 /* Read the ranges property (for regs memory translation) */ 706 cuint = fdt_getprop(fdt, node, "ranges", &len); 707 if (!cuint) 708 panic("missing ranges property"); 709 710 len /= sizeof(*cuint); 711 if (len == 3) 712 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 713 714 fdt_for_each_subnode(b_node, fdt, node) { 715 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 716 if (cuint) { 717 /* 718 * We found a property "gpio-controller" in the node: 719 * the node is a GPIO bank description, add it to the 720 * bank list. 721 */ 722 struct stm32_gpio_bank *bank = NULL; 723 724 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 725 bank_is_registered(fdt, b_node)) 726 continue; 727 728 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 729 range_offs, &bank); 730 if (res) 731 return res; 732 733 /* Registering a provider should not defer probe */ 734 res = gpio_register_provider(fdt, b_node, 735 stm32_gpio_get_dt, bank); 736 if (res) 737 panic(); 738 739 STAILQ_INSERT_TAIL(&bank_list, bank, link); 740 741 if (IS_ENABLED(CFG_STM32MP13)) 742 set_bank_gpio_non_secure(bank); 743 } else { 744 if (len != -FDT_ERR_NOTFOUND) 745 panic(); 746 } 747 } 748 749 return TEE_SUCCESS; 750 } 751 752 #ifndef CFG_DRIVERS_PINCTRL 753 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node, 754 struct stm32_pinctrl *pinctrl, size_t count) 755 { 756 const fdt32_t *cuint = NULL; 757 int lenp = 0; 758 int i = 0; 759 size_t found = 0; 760 761 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp); 762 if (!cuint) 763 return -FDT_ERR_NOTFOUND; 764 765 for (i = 0; i < (lenp / 4); i++) { 766 int node = 0; 767 int subnode = 0; 768 769 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 770 if (node < 0) 771 return -FDT_ERR_NOTFOUND; 772 773 fdt_for_each_subnode(subnode, fdt, node) { 774 size_t n = 0; 775 int rc = 0; 776 777 if (count > found) 778 n = count - found; 779 else 780 n = 0; 781 782 rc = get_pinctrl_from_fdt(fdt, subnode, 783 &pinctrl[found], n); 784 if (rc < 0) 785 return rc; 786 787 found += (size_t)rc; 788 } 789 790 cuint++; 791 } 792 793 return (int)found; 794 } 795 #endif /*CFG_DRIVERS_PINCTRL*/ 796 797 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 798 { 799 int node = 0; 800 const fdt32_t *cuint = NULL; 801 802 fdt_for_each_subnode(node, fdt, pinctrl_node) { 803 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 804 continue; 805 806 cuint = fdt_getprop(fdt, node, "reg", NULL); 807 if (!cuint) 808 continue; 809 810 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 811 continue; 812 813 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 814 if (!cuint) 815 panic(); 816 817 return (int)fdt32_to_cpu(*cuint); 818 } 819 820 return -1; 821 } 822 823 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 824 bool secure) 825 { 826 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 827 uint32_t exceptions = 0; 828 829 if (clk_enable(bank->clock)) 830 panic(); 831 exceptions = cpu_spin_lock_xsave(&gpio_lock); 832 833 if (secure) 834 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 835 else 836 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 837 838 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 839 clk_disable(bank->clock); 840 } 841 842 #ifdef CFG_DRIVERS_PINCTRL 843 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 844 { 845 struct stm32_pinctrl_array *ref = conf->priv; 846 struct stm32_pinctrl *p = ref->pinctrl; 847 size_t pin_count = ref->count; 848 size_t n = 0; 849 850 for (n = 0; n < pin_count; n++) 851 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 852 853 return TEE_SUCCESS; 854 } 855 856 static void stm32_pinctrl_conf_free(struct pinconf *conf) 857 { 858 free(conf); 859 } 860 861 static const struct pinctrl_ops stm32_pinctrl_ops = { 862 .conf_apply = stm32_pinctrl_conf_apply, 863 .conf_free = stm32_pinctrl_conf_free, 864 }; 865 866 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 867 868 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 869 unsigned int *bank, unsigned int *pin, 870 unsigned int *count) 871 { 872 size_t conf_index = 0; 873 size_t pin_count = 0; 874 size_t n = 0; 875 876 assert(count); 877 if (!pinctrl) 878 goto out; 879 880 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 881 struct pinconf *pinconf = pinctrl->confs[conf_index]; 882 struct stm32_pinctrl_array *ref = pinconf->priv; 883 884 /* Consider only the stm32_gpio pins */ 885 if (pinconf->ops != &stm32_pinctrl_ops) 886 continue; 887 888 if (bank || pin) { 889 for (n = 0; n < ref->count; n++) { 890 if (bank && pin_count < *count) 891 bank[pin_count] = ref->pinctrl[n].bank; 892 if (pin && pin_count < *count) 893 pin[pin_count] = ref->pinctrl[n].pin; 894 pin_count++; 895 } 896 } else { 897 pin_count += ref->count; 898 } 899 } 900 901 out: 902 *count = pin_count; 903 } 904 905 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 906 { 907 size_t conf_index = 0; 908 909 if (!pinctrl) 910 return; 911 912 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 913 struct pinconf *pinconf = pinctrl->confs[conf_index]; 914 struct stm32_pinctrl_array *ref = pinconf->priv; 915 struct stm32_pinctrl *pc = NULL; 916 size_t n = 0; 917 918 for (n = 0; n < ref->count; n++) { 919 if (pinconf->ops != &stm32_pinctrl_ops) 920 continue; 921 922 pc = ref->pinctrl + n; 923 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 924 } 925 } 926 } 927 928 /* Allocate and return a pinctrl configuration from a DT reference */ 929 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 930 void *data __unused, 931 struct pinconf **out_pinconf) 932 { 933 struct conf { 934 struct pinconf pinconf; 935 struct stm32_pinctrl_array array_ref; 936 } *loc_conf = NULL; 937 struct stm32_pinctrl *pinctrl = NULL; 938 struct pinconf *pinconf = NULL; 939 const void *fdt = NULL; 940 size_t pin_count = 0; 941 int pinctrl_node = 0; 942 int pinmux_node = 0; 943 int count = 0; 944 945 pinctrl_node = pargs->phandle_node; 946 fdt = pargs->fdt; 947 assert(fdt && pinctrl_node); 948 949 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 950 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 951 pin_count += (size_t)count / sizeof(uint32_t); 952 else if (count != -FDT_ERR_NOTFOUND) 953 panic(); 954 } 955 956 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 957 if (!loc_conf) 958 return TEE_ERROR_OUT_OF_MEMORY; 959 960 pinconf = &loc_conf->pinconf; 961 pinconf->ops = &stm32_pinctrl_ops; 962 pinconf->priv = &loc_conf->array_ref; 963 964 loc_conf->array_ref.count = pin_count; 965 pinctrl = loc_conf->array_ref.pinctrl; 966 967 count = 0; 968 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 969 int found = 0; 970 971 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 972 pin_count - count); 973 if (found <= 0 && found > ((int)pin_count - count)) { 974 /* We can't recover from an error here so let's panic */ 975 panic(); 976 } 977 978 count += found; 979 } 980 981 *out_pinconf = pinconf; 982 983 return TEE_SUCCESS; 984 } 985 #endif /*CFG_DRIVERS_PINCTRL*/ 986 987 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 988 const void *compat_data) 989 { 990 TEE_Result res = TEE_ERROR_GENERIC; 991 992 /* Register GPIO banks described in this pin control node */ 993 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 994 if (res) 995 return res; 996 997 #ifdef CFG_DRIVERS_PINCTRL 998 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 999 (void *)compat_data); 1000 if (res) 1001 return res; 1002 #endif 1003 1004 return TEE_SUCCESS; 1005 } 1006 1007 static const struct dt_device_match stm32_pinctrl_match_table[] = { 1008 { .compatible = "st,stm32mp135-pinctrl" }, 1009 { .compatible = "st,stm32mp157-pinctrl" }, 1010 { .compatible = "st,stm32mp157-z-pinctrl" }, 1011 { } 1012 }; 1013 1014 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 1015 .name = "stm32_gpio-pinctrl", 1016 .type = DT_DRIVER_PINCTRL, 1017 .match_table = stm32_pinctrl_match_table, 1018 .probe = stm32_pinctrl_probe, 1019 }; 1020