xref: /optee_os/core/include/drivers/stm32_gpio.h (revision 70ac0db5f8ba8410b6049ec451febf4561e10ae9)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Copyright (c) 2017-2023, STMicroelectronics
4  */
5 
6 #ifndef DRIVERS_STM32_GPIO_H
7 #define DRIVERS_STM32_GPIO_H
8 
9 #include <assert.h>
10 #include <compiler.h>
11 #include <drivers/pinctrl.h>
12 #include <stdbool.h>
13 #include <stdint.h>
14 #include <stddef.h>
15 
16 #define GPIO_MODE_INPUT		0x0
17 #define GPIO_MODE_OUTPUT	0x1
18 #define GPIO_MODE_ALTERNATE	0x2
19 #define GPIO_MODE_ANALOG	0x3
20 
21 #define GPIO_OTYPE_PUSH_PULL	0x0
22 #define GPIO_OTYPE_OPEN_DRAIN	0x1
23 
24 #define GPIO_OSPEED_LOW		0x0
25 #define GPIO_OSPEED_MEDIUM	0x1
26 #define GPIO_OSPEED_HIGH	0x2
27 #define GPIO_OSPEED_VERY_HIGH	0x3
28 
29 #define GPIO_PUPD_NO_PULL	0x0
30 #define GPIO_PUPD_PULL_UP	0x1
31 #define GPIO_PUPD_PULL_DOWN	0x2
32 
33 #define GPIO_OD_LEVEL_LOW	0x0
34 #define GPIO_OD_LEVEL_HIGH	0x1
35 
36 struct pinctrl_state;
37 
38 /*
39  * GPIO configuration description structured as single 16bit word
40  * for efficient save/restore when GPIO pin suspends or resumes.
41  *
42  * @mode: One of GPIO_MODE_*
43  * @otype: One of GPIO_OTYPE_*
44  * @ospeed: One of GPIO_OSPEED_*
45  * @pupd: One of GPIO_PUPD_*
46  * @od: One of GPIO_OD_*
47  * @af: Alternate function numerical ID between 0 and 15
48  */
49 struct gpio_cfg {
50 	uint16_t mode:		2;
51 	uint16_t otype:		1;
52 	uint16_t ospeed:	2;
53 	uint16_t pupd:		2;
54 	uint16_t od:		1;
55 	uint16_t af:		4;
56 };
57 
58 /*
59  * Description of a pin and its muxing
60  *
61  * @bank: GPIO bank identifier as assigned by the platform
62  * @pin: Pin number in the GPIO bank
63  * ifdef CFG_DRIVERS_PINCTRL
64  * @cfg: Pin configuration
65  * else
66  * @active_cfg: Configuration in active state
67  * @standby_cfg: Configuration in standby state
68  * endif
69  */
70 struct stm32_pinctrl {
71 	uint8_t bank;
72 	uint8_t pin;
73 #ifdef CFG_DRIVERS_PINCTRL
74 	struct gpio_cfg cfg;
75 #else
76 	struct gpio_cfg active_cfg;
77 	struct gpio_cfg standby_cfg;
78 #endif
79 };
80 
81 #ifndef CFG_DRIVERS_PINCTRL
82 /*
83  * Apply series of pin muxing configuration, active state and standby state
84  *
85  * @pinctrl: array of pinctrl references
86  * @count: Number of entries in @pinctrl
87  */
88 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt);
89 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt);
90 
91 /*
92  * Save the current pin configuration as the standby state for a pin series
93  *
94  * @pinctrl: array of pinctrl references
95  * @count: Number of entries in @pinctrl
96  */
97 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt);
98 #endif
99 
100 /*
101  * Save pinctrl instances defined in DT node: identifiers and power states
102  *
103  * @fdt: device tree
104  * @node: device node in the device tree
105  * @pinctrl: NULL or pointer to array of struct stm32_pinctrl
106  * @count: number of elements pointed by argument cfg
107  *
108  * Return the number of pinctrl instances found or a negative value on error.
109  *
110  * When @count is 0, @pinctrl may be NULL. The function will return only the
111  * number of pinctrl instances found in the device tree for the target
112  * device node.
113  *
114  * If more instances than @count are found then the function returns the
115  * effective number of pincltr instance found in the node but fills
116  * output array @pinctrl only for the input @count first entries.
117  */
118 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int node,
119 				  struct stm32_pinctrl *pinctrl, size_t count);
120 
121 #ifdef CFG_STM32_GPIO
122 /*
123  * Configure pin muxing access permission: can be secure or not
124  *
125  * @bank: GPIO bank identifier as assigned by the platform
126  * @pin: Pin number in the GPIO bank
127  * @secure: True if pin is secure, false otherwise
128  */
129 void stm32_gpio_set_secure_cfg(unsigned int bank, unsigned int pin,
130 			       bool secure);
131 #else
132 static inline void stm32_gpio_set_secure_cfg(unsigned int bank __unused,
133 					     unsigned int pin __unused,
134 					     bool secure __unused)
135 {
136 	assert(0);
137 }
138 #endif
139 
140 /*
141  * Get the number of GPIO pins supported by a target GPIO bank
142  *
143  * @fdt: device tree reference
144  * @pinctrl_node: pinctrl node which GPIO bank node belongs to
145  * @bank: target GPIO bank ID
146  * Return number of GPIO pins (>= 0) or a negative value on error
147  */
148 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank);
149 
150 #ifdef CFG_DRIVERS_PINCTRL
151 /*
152  * Get the bank and pin indices related to a pin control state
153  * @pinctrl: Pinctrl state
154  * @bank: Output bank indices array or NULL
155  * @pin: Output pin indices array or NULL
156  * @count: [in] Number of cells of @bank and @pin, [out] pin count in @pinctrl
157  */
158 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl,
159 				 unsigned int *bank, unsigned int *pin,
160 				 unsigned int *count);
161 #else
162 static inline void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *p __unused,
163 					       unsigned int *bank __unused,
164 					       unsigned int *pin __unused,
165 					       unsigned int *count __unused)
166 {
167 }
168 #endif /*CFG_DRIVERS_PINCTRL*/
169 #endif /*DRIVERS_STM32_GPIO_H*/
170