plat-aspeed: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Chia-Wei Wang <chiaw

plat-aspeed: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

show more ...

plat-vexpress: use CFG_AUTO_MAX_PA_BITS on virtual platforms

By default set CFG_AUTO_MAX_PA_BITS=y on the virtual platforms fvp and
qemu_armv8a to allow automatic configuration of the maximal suppor

plat-vexpress: use CFG_AUTO_MAX_PA_BITS on virtual platforms

By default set CFG_AUTO_MAX_PA_BITS=y on the virtual platforms fvp and
qemu_armv8a to allow automatic configuration of the maximal supported
physical address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: add CFG_AUTO_MAX_PA_BITS

Add the configuration variable CFG_AUTO_MAX_PA_BITS that enables
automatic discovery of maximal PA supported by the hardware.

Signed-off-by: Jens Wiklander <jens.wikl

core: add CFG_AUTO_MAX_PA_BITS

Add the configuration variable CFG_AUTO_MAX_PA_BITS that enables
automatic discovery of maximal PA supported by the hardware.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: arm64.h: add read_id_aa64mmfr0_el1()

Add a read function for the system register ID_AA64MMFR0_EL1 and the
mask ID_AA64MMFR0_EL1_PARANGE_MASK to extract the PARange field.

Signed-off-by: Jens

core: arm64.h: add read_id_aa64mmfr0_el1()

Add a read function for the system register ID_AA64MMFR0_EL1 and the
mask ID_AA64MMFR0_EL1_PARANGE_MASK to extract the PARange field.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: fix trace in add_node_to_probe()

Fix trace format, drv_name and node_name are inverted.

Fixes: b3a88b52a17c ("core: dt_driver probe sequence")
Signed-off-by: Gatien Chevallier <gatien.chevall

core: fix trace in add_node_to_probe()

Fix trace format, drv_name and node_name are inverted.

Fixes: b3a88b52a17c ("core: dt_driver probe sequence")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: ffa: return fpi size from FFA_PARTITION_INFO_GET

Until now has FFA_PARTITION_INFO_GET always returned zero in w3, but
FF-A v1.1 requires FFA_PARTITION_INFO_GET to return the size of each
parti

core: ffa: return fpi size from FFA_PARTITION_INFO_GET

Until now has FFA_PARTITION_INFO_GET always returned zero in w3, but
FF-A v1.1 requires FFA_PARTITION_INFO_GET to return the size of each
partition information descriptor returned if
FFA_PARTITION_INFO_GET_COUNT_FLAG isn't set. So fix this by returning
the size of a FF-A v1.1 partition information descriptor in w3.

Fixes: a1c53023cc80 ("core: spmc: support FF-A 1.1")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-stm32mp1: exposes a fastcall SMC watchdog service

Default defines watchdog management SMC based service for non-secure
world to manage the watchdog supervised by OP-TEE secure world.
Non-secure

plat-stm32mp1: exposes a fastcall SMC watchdog service

Default defines watchdog management SMC based service for non-secure
world to manage the watchdog supervised by OP-TEE secure world.
Non-secure world system can leverage this service for example by
enabling a "arm,smc-wdt" compatible node with arm,smc-id=<0xbc000000>
property in its DT.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32mp15: disable non-secure IWDG2 on ST boards

Disable non-secure IWDG2 watchdog device in ST boards stm32mp157a-dk1,
stm32mp157c-dk2, stm32mp157c-ed1 and stm32mp157c-ev1. This watchdog is
fu

dts: stm32mp15: disable non-secure IWDG2 on ST boards

Disable non-secure IWDG2 watchdog device in ST boards stm32mp157a-dk1,
stm32mp157c-dk2, stm32mp157c-ed1 and stm32mp157c-ev1. This watchdog is
fully under control of the non-secure world and OP-TEE is not expected
to interfere with it.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

dts: stm32mp15: enable secure IWDG1 on ST boards

Enable IWDG1 watchdog device in ST boards stm32mp157a-dk1,
stm32mp157c-dk2, stm32mp157c-ed1 and stm32mp157c-ev1.

Reviewed-by: Gatien Chevallier <gat

dts: stm32mp15: enable secure IWDG1 on ST boards

Enable IWDG1 watchdog device in ST boards stm32mp157a-dk1,
stm32mp157c-dk2, stm32mp157c-ed1 and stm32mp157c-ev1.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: arm: rpc_alloc: remove size limit for kernel payload

Removes the size limit of 1 page imposed in
thread_rpc_alloc_kernel_payload(). The purpose of this limit was to
error out early since the k

core: arm: rpc_alloc: remove size limit for kernel payload

Removes the size limit of 1 page imposed in
thread_rpc_alloc_kernel_payload(). The purpose of this limit was to
error out early since the kernel doesn't supply a list of physical pages
and the source of the error is not obvious at first glance. This is
now about to change so remove the limit since the kernel now may
supply the needed list of physical pages.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: rpmb: cleanup useless write_counter in struct rpmb_fat_entry

The write_counter field of the rpmb_fat_entry struct is set from the
RPMB device but never used. Rename it to 'unused' and cleanup

core: rpmb: cleanup useless write_counter in struct rpmb_fat_entry

The write_counter field of the rpmb_fat_entry struct is set from the
RPMB device but never used. Rename it to 'unused' and cleanup the
associated code.

Tested on QEMUv8 with:

$ make CFG_RPMB_FS=y CFG_RPMB_WRITE_KEY=y CFG_RPMB_TESKEY=y check

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp157c-ev1 w/ RPMB)

show more ...

drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jer

drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

show more ...

riscv: virt: Enable CFG_DT

Enable CFG_DT to parse the external DTB passed by previous boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

riscv: virt: Enable CFG_DT

Enable CFG_DT to parse the external DTB passed by previous boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since
we may run SMP system which has multiple harts and thread

riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since
we may run SMP system which has multiple harts and threads.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we

riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we
enable CFG_RISCV_SBI so that OP-TEE utilizes SBI to communicate with
other OS.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

plat-mediatek: disable console when CFG_TEE_CORE_LOG_LEVEL is 0

Following our usage, it can be interesting to disable the console,
typically for a final product.

Acked-by: Jens Wiklander <jens.wikl

plat-mediatek: disable console when CFG_TEE_CORE_LOG_LEVEL is 0

Following our usage, it can be interesting to disable the console,
typically for a final product.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Co-developed-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Julien Masson <jmasson@baylibre.com>

show more ...

plat-stm32mp1: scmi_server: remove useless bounding of voltage levels

Remove bounding of regulators supported voltage levels according
to mix/max levels now that drivers take care of that.

Acked-by

plat-stm32mp1: scmi_server: remove useless bounding of voltage levels

Remove bounding of regulators supported voltage levels according
to mix/max levels now that drivers take care of that.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: regulator: supported voltage consider levels bounds

Assert regulator_supported_voltages() provides a list that takes into
account the min/max voltage levels possibly set from the secure DT.

drivers: regulator: supported voltage consider levels bounds

Assert regulator_supported_voltages() provides a list that takes into
account the min/max voltage levels possibly set from the secure DT.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-stm32mp1: set voltage list at pmic driver init

Bound stm32mp1_pmic supported voltage levels list to min/max voltage
level values set from the DT. This change free quite a bit of byte in
the hea

plat-stm32mp1: set voltage list at pmic driver init

Bound stm32mp1_pmic supported voltage levels list to min/max voltage
level values set from the DT. This change free quite a bit of byte in
the heap for this platform.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: regulator: stm32_vrefbuf: set voltage list at init

Change stm32_vrefbuf driver to set the supported voltage levels list
at driver initialization rather than at first list query.

Acked-by:

drivers: regulator: stm32_vrefbuf: set voltage list at init

Change stm32_vrefbuf driver to set the supported voltage levels list
at driver initialization rather than at first list query.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: update transfer list header and signature

Add tl->flags and TL_FLAGS_HAS_CHECKSUM to align to the latest FW
Handoff spec update.
Bypass checksum verifying and updating if TL_FLAGS_HAS_CHECKSUM

core: update transfer list header and signature

Add tl->flags and TL_FLAGS_HAS_CHECKSUM to align to the latest FW
Handoff spec update.
Bypass checksum verifying and updating if TL_FLAGS_HAS_CHECKSUM bit
is not set in tl->flags.
Update TL signature to 4a0f_b10b to align to the latest FW Handoff
spec update.

Note: It causes Transfer List ABI breakage due to FW Handoff spec
stays with same rev number (v0.9) with above changes.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: remove unused bytes from transfer list

Only marks the minimum bytes required by alignment as 'TL_TAG_EMPTY'
and release the rest of unused bytes from transfer list when downsizing
the data of

core: remove unused bytes from transfer list

Only marks the minimum bytes required by alignment as 'TL_TAG_EMPTY'
and release the rest of unused bytes from transfer list when downsizing
the data of a transfer entry.
Function transfer_list_set_data_size() will remove the unused bytes
from the transfer list so that the freed space is allocable when adding
new transfer entries.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

pta: stats: add commands to print clock and regulator trees

Add statistics PTA commands STATS_CMD_PRINT_DRIVERS_INFO to print
device drivers information on console. The implementation currently
allo

pta: stats: add commands to print clock and regulator trees

Add statistics PTA commands STATS_CMD_PRINT_DRIVERS_INFO to print
device drivers information on console. The implementation currently
allows to print the clock tree and the regulator tree to core console.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so a

core: gic: allow GIC version 1

Before this patch with CFG_ARM_GICV3=n the GIC driver asserted that the
detected GIC version is 2. This is stricter than necessary and breaks
some older platforms so allow version 1 also.

Fixes: 69171bec89ce ("core: gic: check gic version")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Tested-by: Andrew Davis <afd@ti.com>

show more ...

core: gic: make GICR base optional

The physical address of the redistributor was, before this patch, always
used, regardless of whether affinity routing is enabled or otherwise not
needed.

Using th

core: gic: make GICR base optional

The physical address of the redistributor was, before this patch, always
used, regardless of whether affinity routing is enabled or otherwise not
needed.

Using the redistributor is optional if gic_init_donate_sgi_to_ns() isn't
called. So allow the GICR base address to be passed as zero if
gic_init_donate_sgi_to_ns() isn't called. However,
gic_init_donate_sgi_to_ns() will panic if called without a previously
configured GICR base address.

Fixes: 05089e5f9a56 ("core: gic: use redistributor CPU interface")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...