xref: /optee_os/core/drivers/stm32_iwdg.c (revision ec7977328e5715808ba559afd3948acb5806915e) 
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3  * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
4  */
5 
6 #include <assert.h>
7 #include <drivers/clk.h>
8 #include <drivers/clk_dt.h>
9 #include <drivers/stm32_iwdg.h>
10 #include <drivers/wdt.h>
11 #include <io.h>
12 #include <keep.h>
13 #include <kernel/boot.h>
14 #include <kernel/delay.h>
15 #include <kernel/dt.h>
16 #include <kernel/dt_driver.h>
17 #include <kernel/interrupt.h>
18 #include <kernel/misc.h>
19 #include <kernel/panic.h>
20 #include <kernel/pm.h>
21 #include <kernel/spinlock.h>
22 #include <libfdt.h>
23 #include <mm/core_memprot.h>
24 #include <sm/sm.h>
25 #include <stm32_util.h>
26 #include <string.h>
27 #include <trace.h>
28 
29 /* IWDG Compatibility */
30 #define IWDG_TIMEOUT_US		U(1000)
31 #define IWDG_CNT_MASK		GENMASK_32(11, 0)
32 
33 /* IWDG registers offsets */
34 #define IWDG_KR_OFFSET		U(0x00)
35 #define IWDG_PR_OFFSET		U(0x04)
36 #define IWDG_RLR_OFFSET		U(0x08)
37 #define IWDG_SR_OFFSET		U(0x0C)
38 #define IWDG_EWCR_OFFSET	U(0x14)
39 
40 #define IWDG_KR_ACCESS_KEY	U(0x5555)
41 #define IWDG_KR_RELOAD_KEY	U(0xAAAA)
42 #define IWDG_KR_START_KEY	U(0xCCCC)
43 
44 /* Use a fixed prescaler divider of 256 */
45 #define IWDG_PRESCALER_256	U(256)
46 #define IWDG_PR_DIV_256		U(0x06)
47 #define IWDG_PR_DIV_MASK	GENMASK_32(3, 0)
48 
49 #define IWDG_SR_PVU		BIT(0)
50 #define IWDG_SR_RVU		BIT(1)
51 #define IWDG_SR_WVU		BIT(2)
52 #define IWDG_SR_EWU		BIT(3)
53 #define IWDG_SR_UPDATE_MASK	(IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | \
54 				 IWDG_SR_EWU)
55 
56 #define IWDG_EWCR_EWIE		BIT(15)
57 #define IWDG_EWCR_EWIC		BIT(14)
58 
59 /*
60  * Values for struct stm32_iwdg_device::flags
61  * IWDG_FLAGS_HW_ENABLED                Watchdog is enabled by BootROM
62  * IWDG_FLAGS_DISABLE_ON_STOP           Watchdog is freezed in SoC STOP mode
63  * IWDG_FLAGS_DISABLE_ON_STANDBY        Watchdog is freezed in SoC STANDBY mode
64  * IWDG_FLAGS_NON_SECURE                Instance is assigned to non-secure world
65  * IWDG_FLAGS_ENABLED			Watchdog has been enabled
66  */
67 #define IWDG_FLAGS_HW_ENABLED			BIT(0)
68 #define IWDG_FLAGS_DISABLE_ON_STOP		BIT(1)
69 #define IWDG_FLAGS_DISABLE_ON_STANDBY		BIT(2)
70 #define IWDG_FLAGS_NON_SECURE			BIT(3)
71 #define IWDG_FLAGS_ENABLED			BIT(4)
72 
73 /*
74  * IWDG watch instance data
75  * @base - IWDG interface IOMEM base address
76  * @clock - Bus clock
77  * @clk_lsi - IWDG source clock
78  * @flags - Property flags for the IWDG instance
79  * @timeout - Watchdog elaspure timeout
80  * @wdt_chip - Wathcdog chip instance
81  * @link - Link in registered watchdog instance list
82  */
83 struct stm32_iwdg_device {
84 	struct io_pa_va base;
85 	struct clk *clock;
86 	struct clk *clk_lsi;
87 	uint32_t flags;
88 	unsigned long timeout;
89 	struct wdt_chip wdt_chip;
90 	SLIST_ENTRY(stm32_iwdg_device) link;
91 };
92 
93 static SLIST_HEAD(iwdg_dev_list_head, stm32_iwdg_device) iwdg_dev_list =
94 	SLIST_HEAD_INITIALIZER(iwdg_dev_list_head);
95 
96 static vaddr_t get_base(struct stm32_iwdg_device *iwdg)
97 {
98 	return io_pa_or_va(&iwdg->base, 1);
99 }
100 
101 static bool is_assigned_to_nsec(struct stm32_iwdg_device *iwdg)
102 {
103 	return iwdg->flags & IWDG_FLAGS_NON_SECURE;
104 }
105 
106 static bool is_enable(struct stm32_iwdg_device *iwdg)
107 {
108 	return iwdg->flags & IWDG_FLAGS_ENABLED;
109 }
110 
111 /* Return counter value to related to input timeout in seconds, or 0 on error */
112 static uint32_t iwdg_timeout_cnt(struct stm32_iwdg_device *iwdg,
113 				 unsigned long to_sec)
114 {
115 	uint64_t reload = (uint64_t)to_sec * clk_get_rate(iwdg->clk_lsi);
116 	uint64_t cnt = (reload / IWDG_PRESCALER_256) - 1;
117 
118 	/* Be safe and expect any counter to be above 2 */
119 	if (cnt > IWDG_CNT_MASK || cnt < 3)
120 		return 0;
121 
122 	return cnt;
123 }
124 
125 /* Wait IWDG programming completes */
126 static TEE_Result iwdg_wait_sync(struct stm32_iwdg_device *iwdg)
127 {
128 	uint64_t timeout_ref = timeout_init_us(IWDG_TIMEOUT_US);
129 	vaddr_t iwdg_base = get_base(iwdg);
130 
131 	while (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
132 		if (timeout_elapsed(timeout_ref))
133 			break;
134 
135 	if (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
136 		return TEE_ERROR_GENERIC;
137 
138 	return TEE_SUCCESS;
139 }
140 
141 static TEE_Result configure_timeout(struct stm32_iwdg_device *iwdg)
142 {
143 	TEE_Result res = TEE_ERROR_GENERIC;
144 	vaddr_t iwdg_base = get_base(iwdg);
145 	uint32_t rlr_value = 0;
146 
147 	assert(is_enable(iwdg));
148 
149 	rlr_value = iwdg_timeout_cnt(iwdg, iwdg->timeout);
150 	if (!rlr_value)
151 		return TEE_ERROR_GENERIC;
152 
153 	clk_enable(iwdg->clock);
154 
155 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);
156 	io_write32(iwdg_base + IWDG_PR_OFFSET, IWDG_PR_DIV_256);
157 	io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);
158 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
159 
160 	res = iwdg_wait_sync(iwdg);
161 
162 	clk_disable(iwdg->clock);
163 
164 	return res;
165 }
166 
167 static void iwdg_start(struct stm32_iwdg_device *iwdg)
168 {
169 	clk_enable(iwdg->clock);
170 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_START_KEY);
171 	clk_disable(iwdg->clock);
172 
173 	iwdg->flags |= IWDG_FLAGS_ENABLED;
174 }
175 
176 static void iwdg_refresh(struct stm32_iwdg_device *iwdg)
177 {
178 	clk_enable(iwdg->clock);
179 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
180 	clk_disable(iwdg->clock);
181 }
182 
183 /* Operators for watchdog OP-TEE interface */
184 static struct stm32_iwdg_device *wdt_chip_to_iwdg(struct wdt_chip *chip)
185 {
186 	return container_of(chip, struct stm32_iwdg_device, wdt_chip);
187 }
188 
189 static TEE_Result iwdg_wdt_init(struct wdt_chip *chip,
190 				unsigned long *min_timeout,
191 				unsigned long *max_timeout)
192 {
193 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
194 	unsigned long rate = clk_get_rate(iwdg->clk_lsi);
195 
196 	if (!rate)
197 		return TEE_ERROR_GENERIC;
198 
199 	/* Be safe and expect any counter to be above 2 */
200 	*min_timeout = 3 * IWDG_PRESCALER_256 / rate;
201 	*max_timeout = (IWDG_CNT_MASK + 1) * IWDG_PRESCALER_256 / rate;
202 
203 	return TEE_SUCCESS;
204 }
205 
206 static void iwdg_wdt_start(struct wdt_chip *chip)
207 {
208 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
209 
210 	iwdg_start(iwdg);
211 
212 	if (configure_timeout(iwdg))
213 		panic();
214 }
215 
216 static void iwdg_wdt_refresh(struct wdt_chip *chip)
217 {
218 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
219 
220 	iwdg_refresh(iwdg);
221 }
222 
223 static TEE_Result iwdg_wdt_set_timeout(struct wdt_chip *chip,
224 				       unsigned long timeout)
225 {
226 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
227 
228 	if (!iwdg_timeout_cnt(iwdg, timeout))
229 		return TEE_ERROR_BAD_PARAMETERS;
230 
231 	iwdg->timeout = timeout;
232 
233 	if (is_enable(iwdg)) {
234 		TEE_Result res = TEE_ERROR_GENERIC;
235 
236 		res = configure_timeout(iwdg);
237 		if (res)
238 			return res;
239 	}
240 
241 	return TEE_SUCCESS;
242 }
243 
244 static const struct wdt_ops stm32_iwdg_ops = {
245 	.init = iwdg_wdt_init,
246 	.start = iwdg_wdt_start,
247 	.ping = iwdg_wdt_refresh,
248 	.set_timeout = iwdg_wdt_set_timeout,
249 };
250 DECLARE_KEEP_PAGER(stm32_iwdg_ops);
251 
252 /* Driver initialization */
253 static TEE_Result stm32_iwdg_parse_fdt(struct stm32_iwdg_device *iwdg,
254 				       const void *fdt, int node)
255 {
256 	TEE_Result res = TEE_ERROR_GENERIC;
257 	struct dt_node_info dt_info = { };
258 	const fdt32_t *cuint = NULL;
259 
260 	fdt_fill_device_info(fdt, &dt_info, node);
261 
262 	if (dt_info.reg == DT_INFO_INVALID_REG ||
263 	    dt_info.reg_size == DT_INFO_INVALID_REG_SIZE)
264 		panic();
265 
266 	res = clk_dt_get_by_name(fdt, node, "pclk", &iwdg->clock);
267 	if (res)
268 		return res;
269 
270 	res = clk_dt_get_by_name(fdt, node, "lsi", &iwdg->clk_lsi);
271 	if (res)
272 		return res;
273 
274 	if (dt_info.status == DT_STATUS_OK_NSEC)
275 		iwdg->flags |= IWDG_FLAGS_NON_SECURE;
276 
277 	/* Get IOMEM address */
278 	iwdg->base.pa = dt_info.reg;
279 
280 	if (iwdg->flags & IWDG_FLAGS_NON_SECURE)
281 		io_pa_or_va_nsec(&iwdg->base, dt_info.reg_size);
282 	else
283 		io_pa_or_va_secure(&iwdg->base, dt_info.reg_size);
284 
285 	assert(iwdg->base.va);
286 
287 	/* Get and check timeout value */
288 	cuint = fdt_getprop(fdt, node, "timeout-sec", NULL);
289 	if (!cuint)
290 		return TEE_ERROR_BAD_PARAMETERS;
291 
292 	iwdg->timeout = (int)fdt32_to_cpu(*cuint);
293 	if (!iwdg->timeout)
294 		return TEE_ERROR_BAD_PARAMETERS;
295 
296 	if (!iwdg_timeout_cnt(iwdg, iwdg->timeout)) {
297 		EMSG("Timeout %lu not applicable", iwdg->timeout);
298 		return TEE_ERROR_BAD_PARAMETERS;
299 	}
300 
301 	/* DT can specify low power cases */
302 	if (!fdt_getprop(fdt, node, "stm32,enable-on-stop", NULL))
303 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP;
304 
305 	if (!fdt_getprop(fdt, node, "stm32,enable-on-standby", NULL))
306 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;
307 
308 	return TEE_SUCCESS;
309 }
310 
311 /* Platform should override this function to provide IWDG fuses configuration */
312 TEE_Result __weak stm32_get_iwdg_otp_config(paddr_t pbase __unused,
313 					    struct stm32_iwdg_otp_data *otp_d)
314 {
315 	otp_d->hw_enabled = false;
316 	otp_d->disable_on_stop = false;
317 	otp_d->disable_on_standby = false;
318 
319 	return TEE_SUCCESS;
320 }
321 
322 static TEE_Result stm32_iwdg_setup(struct stm32_iwdg_device *iwdg,
323 				   const void *fdt, int node)
324 {
325 	struct stm32_iwdg_otp_data otp_data = { };
326 	TEE_Result res = TEE_SUCCESS;
327 
328 	res = stm32_iwdg_parse_fdt(iwdg, fdt, node);
329 	if (res)
330 		return res;
331 
332 	res = stm32_get_iwdg_otp_config(iwdg->base.pa, &otp_data);
333 	if (res)
334 		return res;
335 
336 	if (otp_data.hw_enabled)
337 		iwdg->flags |= IWDG_FLAGS_HW_ENABLED;
338 	if (otp_data.disable_on_stop)
339 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP;
340 	if (otp_data.disable_on_standby)
341 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;
342 
343 	/* Enable watchdog source clock once for all */
344 	clk_enable(iwdg->clk_lsi);
345 
346 	if (otp_data.hw_enabled) {
347 		iwdg->flags |= IWDG_FLAGS_ENABLED;
348 
349 		/* Configure timeout if watchdog is already enabled */
350 		res = configure_timeout(iwdg);
351 		if (res)
352 			return res;
353 
354 		iwdg_refresh(iwdg);
355 	}
356 
357 	return TEE_SUCCESS;
358 }
359 
360 static TEE_Result stm32_iwdg_register(struct stm32_iwdg_device *iwdg)
361 {
362 	TEE_Result res = TEE_ERROR_GENERIC;
363 
364 	if (is_assigned_to_nsec(iwdg)) {
365 		stm32mp_register_non_secure_periph_iomem(iwdg->base.pa);
366 	} else {
367 		stm32mp_register_secure_periph_iomem(iwdg->base.pa);
368 
369 		/* Expose watchdog runtime service only to secure IWDG */
370 		iwdg->wdt_chip.ops = &stm32_iwdg_ops;
371 
372 		res = watchdog_register(&iwdg->wdt_chip);
373 		if (res)
374 			return res;
375 	}
376 
377 	SLIST_INSERT_HEAD(&iwdg_dev_list, iwdg, link);
378 
379 	return TEE_SUCCESS;
380 }
381 
382 static TEE_Result stm32_iwdg_probe(const void *fdt, int node,
383 				   const void *compat_data __unused)
384 {
385 	struct stm32_iwdg_device *iwdg = NULL;
386 	TEE_Result res = TEE_SUCCESS;
387 
388 	iwdg = calloc(1, sizeof(*iwdg));
389 	if (!iwdg)
390 		return TEE_ERROR_OUT_OF_MEMORY;
391 
392 	res = stm32_iwdg_setup(iwdg, fdt, node);
393 	if (res)
394 		goto err;
395 
396 	res = stm32_iwdg_register(iwdg);
397 	if (res)
398 		goto err;
399 
400 	return TEE_SUCCESS;
401 
402 err:
403 	free(iwdg);
404 	return res;
405 }
406 
407 static const struct dt_device_match stm32_iwdg_match_table[] = {
408 	{ .compatible = "st,stm32mp1-iwdg" },
409 	{ }
410 };
411 
412 DEFINE_DT_DRIVER(stm32_iwdg_dt_driver) = {
413 	.name = "stm32-iwdg",
414 	.match_table = stm32_iwdg_match_table,
415 	.probe = stm32_iwdg_probe,
416 };
417