xref: /optee_os/core/drivers/stm32_iwdg.c (revision 36d2a417f454c515518c77a370b18f4d79ec97b1) 
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3  * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
4  */
5 
6 #include <assert.h>
7 #include <drivers/clk.h>
8 #include <drivers/clk_dt.h>
9 #include <drivers/stm32_iwdg.h>
10 #include <drivers/wdt.h>
11 #include <io.h>
12 #include <keep.h>
13 #include <kernel/boot.h>
14 #include <kernel/delay.h>
15 #include <kernel/dt.h>
16 #include <kernel/dt_driver.h>
17 #include <kernel/interrupt.h>
18 #include <kernel/misc.h>
19 #include <kernel/panic.h>
20 #include <kernel/pm.h>
21 #include <kernel/spinlock.h>
22 #include <libfdt.h>
23 #include <mm/core_memprot.h>
24 #include <sm/sm.h>
25 #include <stm32_util.h>
26 #include <string.h>
27 #include <trace.h>
28 
29 /* IWDG Compatibility */
30 #define IWDG_TIMEOUT_US		U(1000)
31 #define IWDG_CNT_MASK		GENMASK_32(11, 0)
32 
33 /* IWDG registers offsets */
34 #define IWDG_KR_OFFSET		U(0x00)
35 #define IWDG_PR_OFFSET		U(0x04)
36 #define IWDG_RLR_OFFSET		U(0x08)
37 #define IWDG_SR_OFFSET		U(0x0C)
38 #define IWDG_EWCR_OFFSET	U(0x14)
39 
40 #define IWDG_KR_ACCESS_KEY	U(0x5555)
41 #define IWDG_KR_RELOAD_KEY	U(0xAAAA)
42 #define IWDG_KR_START_KEY	U(0xCCCC)
43 
44 /* Use a fixed prescaler divider of 256 */
45 #define IWDG_PRESCALER_256	U(256)
46 #define IWDG_PR_DIV_256		U(0x06)
47 #define IWDG_PR_DIV_MASK	GENMASK_32(3, 0)
48 
49 #define IWDG_SR_PVU		BIT(0)
50 #define IWDG_SR_RVU		BIT(1)
51 #define IWDG_SR_WVU		BIT(2)
52 #define IWDG_SR_EWU		BIT(3)
53 #define IWDG_SR_UPDATE_MASK	(IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | \
54 				 IWDG_SR_EWU)
55 
56 #define IWDG_EWCR_EWIE		BIT(15)
57 #define IWDG_EWCR_EWIC		BIT(14)
58 
59 /*
60  * Values for struct stm32_iwdg_device::flags
61  * IWDG_FLAGS_HW_ENABLED                Watchdog is enabled by BootROM
62  * IWDG_FLAGS_DISABLE_ON_STOP           Watchdog is freezed in SoC STOP mode
63  * IWDG_FLAGS_DISABLE_ON_STANDBY        Watchdog is freezed in SoC STANDBY mode
64  * IWDG_FLAGS_NON_SECURE                Instance is assigned to non-secure world
65  * IWDG_FLAGS_ENABLED			Watchdog has been enabled
66  */
67 #define IWDG_FLAGS_HW_ENABLED			BIT(0)
68 #define IWDG_FLAGS_DISABLE_ON_STOP		BIT(1)
69 #define IWDG_FLAGS_DISABLE_ON_STANDBY		BIT(2)
70 #define IWDG_FLAGS_NON_SECURE			BIT(3)
71 #define IWDG_FLAGS_ENABLED			BIT(4)
72 
73 /*
74  * IWDG watch instance data
75  * @base - IWDG interface IOMEM base address
76  * @clk_pclk - Bus clock
77  * @clk_lsi - IWDG source clock
78  * @flags - Property flags for the IWDG instance
79  * @timeout - Watchdog elaspure timeout
80  * @wdt_chip - Wathcdog chip instance
81  * @link - Link in registered watchdog instance list
82  */
83 struct stm32_iwdg_device {
84 	struct io_pa_va base;
85 	struct clk *clk_pclk;
86 	struct clk *clk_lsi;
87 	uint32_t flags;
88 	unsigned long timeout;
89 	struct wdt_chip wdt_chip;
90 	SLIST_ENTRY(stm32_iwdg_device) link;
91 };
92 
93 static SLIST_HEAD(iwdg_dev_list_head, stm32_iwdg_device) iwdg_dev_list =
94 	SLIST_HEAD_INITIALIZER(iwdg_dev_list_head);
95 
96 static vaddr_t get_base(struct stm32_iwdg_device *iwdg)
97 {
98 	return io_pa_or_va(&iwdg->base, 1);
99 }
100 
101 static bool is_assigned_to_nsec(struct stm32_iwdg_device *iwdg)
102 {
103 	return iwdg->flags & IWDG_FLAGS_NON_SECURE;
104 }
105 
106 static bool is_enable(struct stm32_iwdg_device *iwdg)
107 {
108 	return iwdg->flags & IWDG_FLAGS_ENABLED;
109 }
110 
111 /* Return counter value to related to input timeout in seconds, or 0 on error */
112 static uint32_t iwdg_timeout_cnt(struct stm32_iwdg_device *iwdg,
113 				 unsigned long to_sec)
114 {
115 	uint64_t reload = (uint64_t)to_sec * clk_get_rate(iwdg->clk_lsi);
116 	uint64_t cnt = (reload / IWDG_PRESCALER_256) - 1;
117 
118 	/* Be safe and expect any counter to be above 2 */
119 	if (cnt > IWDG_CNT_MASK || cnt < 3)
120 		return 0;
121 
122 	return cnt;
123 }
124 
125 /* Wait IWDG programming completes */
126 static TEE_Result iwdg_wait_sync(struct stm32_iwdg_device *iwdg)
127 {
128 	uint64_t timeout_ref = timeout_init_us(IWDG_TIMEOUT_US);
129 	vaddr_t iwdg_base = get_base(iwdg);
130 
131 	while (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
132 		if (timeout_elapsed(timeout_ref))
133 			break;
134 
135 	if (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
136 		return TEE_ERROR_GENERIC;
137 
138 	return TEE_SUCCESS;
139 }
140 
141 static TEE_Result configure_timeout(struct stm32_iwdg_device *iwdg)
142 {
143 	TEE_Result res = TEE_ERROR_GENERIC;
144 	vaddr_t iwdg_base = get_base(iwdg);
145 	uint32_t rlr_value = 0;
146 
147 	assert(is_enable(iwdg));
148 
149 	rlr_value = iwdg_timeout_cnt(iwdg, iwdg->timeout);
150 	if (!rlr_value)
151 		return TEE_ERROR_GENERIC;
152 
153 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);
154 	io_write32(iwdg_base + IWDG_PR_OFFSET, IWDG_PR_DIV_256);
155 	io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);
156 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
157 
158 	res = iwdg_wait_sync(iwdg);
159 
160 	return res;
161 }
162 
163 static void iwdg_start(struct stm32_iwdg_device *iwdg)
164 {
165 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_START_KEY);
166 
167 	iwdg->flags |= IWDG_FLAGS_ENABLED;
168 }
169 
170 static void iwdg_refresh(struct stm32_iwdg_device *iwdg)
171 {
172 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
173 }
174 
175 /* Operators for watchdog OP-TEE interface */
176 static struct stm32_iwdg_device *wdt_chip_to_iwdg(struct wdt_chip *chip)
177 {
178 	return container_of(chip, struct stm32_iwdg_device, wdt_chip);
179 }
180 
181 static TEE_Result iwdg_wdt_init(struct wdt_chip *chip,
182 				unsigned long *min_timeout,
183 				unsigned long *max_timeout)
184 {
185 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
186 	unsigned long rate = clk_get_rate(iwdg->clk_lsi);
187 
188 	if (!rate)
189 		return TEE_ERROR_GENERIC;
190 
191 	/* Be safe and expect any counter to be above 2 */
192 	*min_timeout = 3 * IWDG_PRESCALER_256 / rate;
193 	*max_timeout = (IWDG_CNT_MASK + 1) * IWDG_PRESCALER_256 / rate;
194 
195 	return TEE_SUCCESS;
196 }
197 
198 static void iwdg_wdt_start(struct wdt_chip *chip)
199 {
200 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
201 
202 	iwdg_start(iwdg);
203 
204 	if (configure_timeout(iwdg))
205 		panic();
206 }
207 
208 static void iwdg_wdt_refresh(struct wdt_chip *chip)
209 {
210 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
211 
212 	iwdg_refresh(iwdg);
213 }
214 
215 static TEE_Result iwdg_wdt_set_timeout(struct wdt_chip *chip,
216 				       unsigned long timeout)
217 {
218 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
219 
220 	if (!iwdg_timeout_cnt(iwdg, timeout))
221 		return TEE_ERROR_BAD_PARAMETERS;
222 
223 	iwdg->timeout = timeout;
224 
225 	if (is_enable(iwdg)) {
226 		TEE_Result res = TEE_ERROR_GENERIC;
227 
228 		res = configure_timeout(iwdg);
229 		if (res)
230 			return res;
231 	}
232 
233 	return TEE_SUCCESS;
234 }
235 
236 static const struct wdt_ops stm32_iwdg_ops = {
237 	.init = iwdg_wdt_init,
238 	.start = iwdg_wdt_start,
239 	.ping = iwdg_wdt_refresh,
240 	.set_timeout = iwdg_wdt_set_timeout,
241 };
242 DECLARE_KEEP_PAGER(stm32_iwdg_ops);
243 
244 /* Driver initialization */
245 static TEE_Result stm32_iwdg_parse_fdt(struct stm32_iwdg_device *iwdg,
246 				       const void *fdt, int node)
247 {
248 	TEE_Result res = TEE_ERROR_GENERIC;
249 	struct dt_node_info dt_info = { };
250 	const fdt32_t *cuint = NULL;
251 
252 	fdt_fill_device_info(fdt, &dt_info, node);
253 
254 	if (dt_info.reg == DT_INFO_INVALID_REG ||
255 	    dt_info.reg_size == DT_INFO_INVALID_REG_SIZE)
256 		panic();
257 
258 	res = clk_dt_get_by_name(fdt, node, "pclk", &iwdg->clk_pclk);
259 	if (res)
260 		return res;
261 
262 	res = clk_dt_get_by_name(fdt, node, "lsi", &iwdg->clk_lsi);
263 	if (res)
264 		return res;
265 
266 	if (dt_info.status == DT_STATUS_OK_NSEC)
267 		iwdg->flags |= IWDG_FLAGS_NON_SECURE;
268 
269 	/* Get IOMEM address */
270 	iwdg->base.pa = dt_info.reg;
271 
272 	if (iwdg->flags & IWDG_FLAGS_NON_SECURE)
273 		io_pa_or_va_nsec(&iwdg->base, dt_info.reg_size);
274 	else
275 		io_pa_or_va_secure(&iwdg->base, dt_info.reg_size);
276 
277 	assert(iwdg->base.va);
278 
279 	/* Get and check timeout value */
280 	cuint = fdt_getprop(fdt, node, "timeout-sec", NULL);
281 	if (!cuint)
282 		return TEE_ERROR_BAD_PARAMETERS;
283 
284 	iwdg->timeout = (int)fdt32_to_cpu(*cuint);
285 	if (!iwdg->timeout)
286 		return TEE_ERROR_BAD_PARAMETERS;
287 
288 	if (!iwdg_timeout_cnt(iwdg, iwdg->timeout)) {
289 		EMSG("Timeout %lu not applicable", iwdg->timeout);
290 		return TEE_ERROR_BAD_PARAMETERS;
291 	}
292 
293 	/* DT can specify low power cases */
294 	if (!fdt_getprop(fdt, node, "stm32,enable-on-stop", NULL))
295 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP;
296 
297 	if (!fdt_getprop(fdt, node, "stm32,enable-on-standby", NULL))
298 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;
299 
300 	return TEE_SUCCESS;
301 }
302 
303 /* Platform should override this function to provide IWDG fuses configuration */
304 TEE_Result __weak stm32_get_iwdg_otp_config(paddr_t pbase __unused,
305 					    struct stm32_iwdg_otp_data *otp_d)
306 {
307 	otp_d->hw_enabled = false;
308 	otp_d->disable_on_stop = false;
309 	otp_d->disable_on_standby = false;
310 
311 	return TEE_SUCCESS;
312 }
313 
314 static TEE_Result stm32_iwdg_setup(struct stm32_iwdg_device *iwdg,
315 				   const void *fdt, int node)
316 {
317 	struct stm32_iwdg_otp_data otp_data = { };
318 	TEE_Result res = TEE_SUCCESS;
319 
320 	res = stm32_iwdg_parse_fdt(iwdg, fdt, node);
321 	if (res)
322 		return res;
323 
324 	res = stm32_get_iwdg_otp_config(iwdg->base.pa, &otp_data);
325 	if (res)
326 		return res;
327 
328 	if (otp_data.hw_enabled)
329 		iwdg->flags |= IWDG_FLAGS_HW_ENABLED;
330 	if (otp_data.disable_on_stop)
331 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP;
332 	if (otp_data.disable_on_standby)
333 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;
334 
335 	/* Enable watchdog source and bus clocks once for all */
336 	clk_enable(iwdg->clk_lsi);
337 	clk_enable(iwdg->clk_pclk);
338 
339 	if (otp_data.hw_enabled) {
340 		iwdg->flags |= IWDG_FLAGS_ENABLED;
341 
342 		/* Configure timeout if watchdog is already enabled */
343 		res = configure_timeout(iwdg);
344 		if (res)
345 			return res;
346 
347 		iwdg_refresh(iwdg);
348 	}
349 
350 	return TEE_SUCCESS;
351 }
352 
353 static TEE_Result stm32_iwdg_register(struct stm32_iwdg_device *iwdg)
354 {
355 	TEE_Result res = TEE_ERROR_GENERIC;
356 
357 	if (is_assigned_to_nsec(iwdg)) {
358 		stm32mp_register_non_secure_periph_iomem(iwdg->base.pa);
359 	} else {
360 		stm32mp_register_secure_periph_iomem(iwdg->base.pa);
361 
362 		/* Expose watchdog runtime service only to secure IWDG */
363 		iwdg->wdt_chip.ops = &stm32_iwdg_ops;
364 
365 		res = watchdog_register(&iwdg->wdt_chip);
366 		if (res)
367 			return res;
368 	}
369 
370 	SLIST_INSERT_HEAD(&iwdg_dev_list, iwdg, link);
371 
372 	return TEE_SUCCESS;
373 }
374 
375 static TEE_Result stm32_iwdg_probe(const void *fdt, int node,
376 				   const void *compat_data __unused)
377 {
378 	struct stm32_iwdg_device *iwdg = NULL;
379 	TEE_Result res = TEE_SUCCESS;
380 
381 	iwdg = calloc(1, sizeof(*iwdg));
382 	if (!iwdg)
383 		return TEE_ERROR_OUT_OF_MEMORY;
384 
385 	res = stm32_iwdg_setup(iwdg, fdt, node);
386 	if (res)
387 		goto err;
388 
389 	res = stm32_iwdg_register(iwdg);
390 	if (res)
391 		goto err;
392 
393 	return TEE_SUCCESS;
394 
395 err:
396 	free(iwdg);
397 	return res;
398 }
399 
400 static const struct dt_device_match stm32_iwdg_match_table[] = {
401 	{ .compatible = "st,stm32mp1-iwdg" },
402 	{ }
403 };
404 
405 DEFINE_DT_DRIVER(stm32_iwdg_dt_driver) = {
406 	.name = "stm32-iwdg",
407 	.match_table = stm32_iwdg_match_table,
408 	.probe = stm32_iwdg_probe,
409 };
410