| 4b46e0e8 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: mailbox communication
Mailbox driver to communicate with the PLM firmware executing on the
Microblaze processor.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: J
drivers: versal: mailbox communication
Mailbox driver to communicate with the PLM firmware executing on the
Microblaze processor.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 3a340005 | 12-Sep-2022 |
Andrew Mustea <andrew.mustea@microsoft.com> |
core: drivers: nxp: Add LX2160A-series SecMon driver
- This driver implements reading the entire NXP LX2160-series Security
Monitor (SecMon) module.
- To enable the SecMon driver, the optee-os bui
core: drivers: nxp: Add LX2160A-series SecMon driver
- This driver implements reading the entire NXP LX2160-series Security
Monitor (SecMon) module.
- To enable the SecMon driver, the optee-os build requires the
CFG_LS_SEC_MON flag.
Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| b46e2b4d | 22-Aug-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
dt-bindings: define system reset controller for stm32mp1 flavors
Define DT binding ID related to system reset controller, for both
STM32MP15 and STM32MP13 variants.
Acked-by: Jens Wiklander <jens.w
dt-bindings: define system reset controller for stm32mp1 flavors
Define DT binding ID related to system reset controller, for both
STM32MP15 and STM32MP13 variants.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 4afbdbdd | 01-Aug-2022 |
Anton Eliasson <anton.eliasson@axis.com> |
drivers: scmi-msg: Propagate errors from platform voltd_get_level
plat_scmi_voltd_get_level is refactored to return an SCMI error code and
retrieve the voltage via an out parameter. This allows erro
drivers: scmi-msg: Propagate errors from platform voltd_get_level
plat_scmi_voltd_get_level is refactored to return an SCMI error code and
retrieve the voltage via an out parameter. This allows errors from the
platform SCMI server implementation to be propagated to the REE.
The implementation for stm32mp1 is updated to handle at least some
possible errors.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Anton Eliasson <anton.eliasson@axis.com>
show more ...
|
| cd495a5a | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: versal: general purpose i/o
Provide access to the GPIO controller on Versal ACAP.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.or
drivers: versal: general purpose i/o
Provide access to the GPIO controller on Versal ACAP.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 9756bcc4 | 24-Feb-2022 |
Clement Faure <clement.faure@nxp.com> |
core: driver: add common i.MX MU driver
Add a common MU driver for i.MX platforms. This MU driver is used to
communicate with external security controllers.
This driver includes a generic part and
core: driver: add common i.MX MU driver
Add a common MU driver for i.MX platforms. This MU driver is used to
communicate with external security controllers.
This driver includes a generic part and an hardware abstraction layer
for low level MU functions.
The MU driver implements the HAL for the following platforms:
- mx8ulpevk
- mx8qmmek/imx8qxpmek
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| dfeed924 | 07-May-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_huk: Add AES eFuse and HUK seed support
When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption
drivers: zynqmp_huk: Add AES eFuse and HUK seed support
When AES eFuse is used to encrypt boot loaders and bitstreams then PUF
functionality is not available for use. When AES eFuse based encryption is
in use AES eFuse key becomes device key instead of PUF generated key.
In order to re-plenish additional device specific entropy that PUF would
provide utilize selected set of User programmable eFuses.
Selected user eFuses should be programmed during device manufacturing with
cryptographically good random numbers.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 214ee971 | 27-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zymqmp_pm: add USER eFuse support
Adds necessary defines for accessing USER eFuses.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.car
drivers: zymqmp_pm: add USER eFuse support
Adds necessary defines for accessing USER eFuses.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 6e96536e | 30-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_pm: Add eFuse programming support
Add support to program eFuses utiling functionality found in PMU firmware.
If eFuse programming functionality has been disabled in PMU firmware the
drivers: zynqmp_pm: Add eFuse programming support
Add support to program eFuses utiling functionality found in PMU firmware.
If eFuse programming functionality has been disabled in PMU firmware then
programming will fail.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 97558570 | 29-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
drivers: zynqmp_pm: fix cache alignment for eFuse operation
Allocate cache aligned temporary memory for both eFuse operation request
and data buffer to make sure that operation is always cache align
drivers: zynqmp_pm: fix cache alignment for eFuse operation
Allocate cache aligned temporary memory for both eFuse operation request
and data buffer to make sure that operation is always cache aligned and to
make usage easier.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 4682bf0f | 30-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
core: add allocator for cache aligned memory
Provides new common maximum cache line aligned allocator for allocating
memory to be used when communicating with different peripherals within the
CPU.
core: add allocator for cache aligned memory
Provides new common maximum cache line aligned allocator for allocating
memory to be used when communicating with different peripherals within the
CPU.
Allocated memory can be readily used with cache maintenance operations.
This is based on core/drivers/imx/dcp/dcp_utils.c.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 3077e812 | 26-Jul-2022 |
Clement Faure <clement.faure@nxp.com> |
core: mm: return true for mattr_is_cached() and TEE_MATTR_MEM_TYPE_TAGGED
Memory areas tagged with TEE_MATTR_MEM_TYPE_TAGGED attributes are
cached. Modify mattr_is_cached() accordingly.
Fixes: 7c3a
core: mm: return true for mattr_is_cached() and TEE_MATTR_MEM_TYPE_TAGGED
Memory areas tagged with TEE_MATTR_MEM_TYPE_TAGGED attributes are
cached. Modify mattr_is_cached() accordingly.
Fixes: 7c3ab7744d ("core: mm: add TEE_MATTR_MEM_TYPE_TAGGED")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 48ca91ed | 31-Mar-2021 |
Vahid Dukandar <vahidd@microsoft.com> |
drivers: bcm_sotp: add sotp write support
- Added write support for bcm secure one time programmable fuses.
- bcm_iproc_sotp_mem_read() now takes in a bool value for sotp_add_ecc
instead of an int
drivers: bcm_sotp: add sotp write support
- Added write support for bcm secure one time programmable fuses.
- bcm_iproc_sotp_mem_read() now takes in a bool value for sotp_add_ecc
instead of an int to denote if error checking memory is supported.
- Updated debug and error messages to return TEE_result codes.
Signed-off-by: Vahid Dukandar <vahidd@microsoft.com>
Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| c30ae302 | 14-Jul-2022 |
Johann Neuhauser <jneuhauser@dh-electronics.com> |
dt-bindings: gpio: add GPIO_PULL_{UP,DOWN} definitions
This is required to bump stm32mp15 dts(i) files to Linux 5.19-rc6.
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Reviewed-by
dt-bindings: gpio: add GPIO_PULL_{UP,DOWN} definitions
This is required to bump stm32mp15 dts(i) files to Linux 5.19-rc6.
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 4a3e6b90 | 29-Apr-2022 |
Andrew Davis <afd@ti.com> |
core: rng_hw: Remove hw_get_random_byte()
Now that all everyone is moved over to hw_get_random_bytes()
we can remove the stub hw_get_random_byte() and the weak default
hw_get_random_bytes().
Signed
core: rng_hw: Remove hw_get_random_byte()
Now that all everyone is moved over to hw_get_random_bytes()
we can remove the stub hw_get_random_byte() and the weak default
hw_get_random_bytes().
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 391a3854 | 29-Apr-2022 |
Andrew Davis <afd@ti.com> |
core: Add hw_get_random_bytes()
Currently there are two options for supporting hardware RNG, implementing
hw_get_random_byte() or overriding crypto_rng_read().
crypto_rng_read() is provided by eith
core: Add hw_get_random_bytes()
Currently there are two options for supporting hardware RNG, implementing
hw_get_random_byte() or overriding crypto_rng_read().
crypto_rng_read() is provided by either a software PRNG or by a hardware
RNG through a weak function in rng_hw.c. This weak function repeatedly
calls hw_get_random_byte(). This can be an unneeded slowdown for
platforms that fetch more than one byte of randomness per call to their
HW RNG (all of them). The usual pattern is to store these extra bytes
in a FIFO and feed them out one at a time. But since the only two callers
of hw_get_random_byte() are themselves users of more than one byte this
indirection is unnecessary. To get around this some platforms have also
started overriding crypto_rng_read() which makes the API flow a bit less
intuitive than it could be.
Plan here is that platforms only need to implement hw_get_random_bytes().
This can be called with length = 1 if we only need a single byte. But in
the more common case we get a performance boost and simplify the RNG call
flow.
To start we keep hw_get_random_byte() and have the new
hw_get_random_bytes() use it to get platform HW RNG byte at a time.
When we finish moving all plats over to hw_get_random_bytes() then
hw_get_random_byte() can be removed.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| dc357ecd | 06-Jul-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: scmi_server update for STM32MP13
Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.
This change also remove the '0' index to the SCMI domains
plat-stm32mp1: scmi_server update for STM32MP13
Update the SCMI server to support STM32MP13 and its SCMI domains: clock,
reset and voltage.
This change also remove the '0' index to the SCMI domains in order to
align with Linux kernel.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 10f7f1fd | 06-Jul-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
dt-bindings: add STM32MP13 regulator bindings
These bindings will be used for the SCMI voltage domain.
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien
dt-bindings: add STM32MP13 regulator bindings
These bindings will be used for the SCMI voltage domain.
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 7968bdf6 | 28-Jun-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: stm32_rng: don't export stm32_rng_read_raw()
No need to export stm32_rng function stm32_rng_read_raw(). It is only
called from stm32_rng_read(). Also removes re-enabling of RNG in
stm32_rng
drivers: stm32_rng: don't export stm32_rng_read_raw()
No need to export stm32_rng function stm32_rng_read_raw(). It is only
called from stm32_rng_read(). Also removes re-enabling of RNG in
stm32_rng_read_raw() since already handled by caller function.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 3fc5c287 | 13-May-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: imx: dcp: disable the use of UNIQUE KEY after HUK generation
Disable the use of DCP unique key (0xfe in the DCP key selection) after
the HUK generation.
The DCP unique key is used to genera
drivers: imx: dcp: disable the use of UNIQUE KEY after HUK generation
Disable the use of DCP unique key (0xfe in the DCP key selection) after
the HUK generation.
The DCP unique key is used to generate the HUK at boot time. Disabling
the use of the unique key prevents the non-secure world from
re-generating the HUK.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Ricardo Salveti <ricardo@foundries.io> (imx-mx6ullevk)
show more ...
|
| 1e1e5a4d | 07-Jun-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_shared_io: introduce shared io driver
This commit implements shared registers support, previously handled in
core/arch/arm/plat-stm32mp1/shared_resources.c, at platform level.
Defaul
drivers: stm32_shared_io: introduce shared io driver
This commit implements shared registers support, previously handled in
core/arch/arm/plat-stm32mp1/shared_resources.c, at platform level.
Default enable CFG_STM32_SHARED_IO.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 505c8fc4 | 07-Jun-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: handle large holes in S-EL0 map
Prior to this patch it was assumed that the memory map of a user mode
context had no holes or very small holes. This leads to a higher pressure
on the translati
core: handle large holes in S-EL0 map
Prior to this patch it was assumed that the memory map of a user mode
context had no holes or very small holes. This leads to a higher pressure
on the translation tables than necessary.
So fix this by skipping to allocate translation tables for holes in the
memory map of a user mode context where possible.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 3a5e9803 | 07-Jun-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: remove SCMI0 channel index
Removes index 0 from SCMI DT binding ID macros and driver labels to
synchronize with Linux kernel 5.18 that considers a single SCMI
channel, see [1] and [2]
plat-stm32mp1: remove SCMI0 channel index
Removes index 0 from SCMI DT binding ID macros and driver labels to
synchronize with Linux kernel 5.18 that considers a single SCMI
channel, see [1] and [2].
Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-4-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-5-alexandre.torgue@foss.st.com
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| b12fd496 | 13-Jun-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: scmi_server: removed unused channel SCMI1
Remove this SCMI channel from DT bindings and platform driver as it is
unused.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.c
plat-stm32mp1: scmi_server: removed unused channel SCMI1
Remove this SCMI channel from DT bindings and platform driver as it is
unused.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| db592d4d | 13-Jun-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: drivers: update stm32mp_dt_bindings.h
Adds st,stm32mp15-regulator.h to the header files included for
stm32mp15 as these bindings are used for SCMI services.
Signed-off-by: Gatien Chevallier <
core: drivers: update stm32mp_dt_bindings.h
Adds st,stm32mp15-regulator.h to the header files included for
stm32mp15 as these bindings are used for SCMI services.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|