drivers: crypto: stm32: fix SAES driver set_field_u32 usage

set_field_u32() is a function that allows you to change a specific bit
in a register by using a mask. The function returns the full value

drivers: crypto: stm32: fix SAES driver set_field_u32 usage

set_field_u32() is a function that allows you to change a specific bit
in a register by using a mask. The function returns the full value of
the register, which means that the use of bitwise OR here is a mistake.
The current code works here only because the modified registers are
initialized. Moreover, I've reverted a commit as there is no
need to shift the value as the function already does it.

Fix the usage of the function in the SAES driver by replacing
bitwise OR assignments with simple assignments.

Fixes: c83a542f3734 ("drivers: crypto: stm32: fix SAES key selection")
Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: update clock and power management

Better handle clock and reset resources by implementing
enable_rng_clock()/disable_rng_clock(). Do not implement a PM callback
if OP-TEE runs wi

drivers: stm32_rng: update clock and power management

Better handle clock and reset resources by implementing
enable_rng_clock()/disable_rng_clock(). Do not implement a PM callback
if OP-TEE runs with a software RNG. Finally, implement shared resource
management only for stm32mp15x platforms as it is not used on other
platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: restrain access on non secure peripherals for OP-TEE

Implement a driver specific firewall bus probe that will
only probe secure peripherals and implement firewall exceptions fo

drivers: stm32_rifsc: restrain access on non secure peripherals for OP-TEE

Implement a driver specific firewall bus probe that will
only probe secure peripherals and implement firewall exceptions for
which no firewall operations will be done when CFG_INSECURE is set.
This allows, for example, to share a console with the non-secure world
for development purposes.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: update RIFSC as a firewall controller

Use the new firewall API to populate the firewall bus and register
the RIFSC as a firewall provider.

While there, update device tree RIF

drivers: stm32_rifsc: update RIFSC as a firewall controller

Use the new firewall API to populate the firewall bus and register
the RIFSC as a firewall provider.

While there, update device tree RIF macros and sort them in the correct
files. Register bit-field macros should be present in the driver while
device tree macros should be present in device tree bindings files.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: remove firewall_dt_probe_bus()

Remove firewall_dt_probe_bus() from the firewall framework as it seems
unlikely that we can have a consensual implementation of this feature.

Signe

drivers: firewall: remove firewall_dt_probe_bus()

Remove firewall_dt_probe_bus() from the firewall framework as it seems
unlikely that we can have a consensual implementation of this feature.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: add stm32_risaf driver

Add the stm32_risaf driver to handle all RISAFs instances on a SoC.
Through RISAF registers, a trusted domain application, or the application
to whom the co

drivers: firewall: add stm32_risaf driver

Add the stm32_risaf driver to handle all RISAFs instances on a SoC.
Through RISAF registers, a trusted domain application, or the application
to whom the configuration has been delegated, assigns memory regions to
one or more security domains (secure, privilege, compartment).
RISAF4 includes the DDR memory cipher engine (DDRMCE) feature.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32-core: set clock number to 0 if node is not found

If fdt_clk_stm32_parse_by_name() is called for a clock node that is not
present, the fdt_getprop() may return an error value for len. In t

clk: stm32-core: set clock number to 0 if node is not found

If fdt_clk_stm32_parse_by_name() is called for a clock node that is not
present, the fdt_getprop() may return an error value for len. In this
case, set *nb to 0 instead of returning an error code.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Gabriel FERNANDEZ <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: implement multi-gate management at core level

The majority of all peripherals have their bus and kernel clocks with
the same clock gating register bit. Therefore it is mandatory to handle
a cou

clk: implement multi-gate management at core level

The majority of all peripherals have their bus and kernel clocks with
the same clock gating register bit. Therefore it is mandatory to handle
a counter on the gates.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp1: add dsb in clock driver

Add memory barriers in RCC clock driver to ensure the system is in the
expected state when requests are proceeded by RCC. No pending register
operation before

clk: stm32mp1: add dsb in clock driver

Add memory barriers in RCC clock driver to ensure the system is in the
expected state when requests are proceeded by RCC. No pending register
operation before disabling the clocks and return to caller only when
clock is enabled, so before any accesses to the clocked devices.

As the registers are mapped as device memory (shareable, bufferable),
the order of operation is guaranteed only at outer shareable limit
and not on each device, for example when they are not on the same bus.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: save/restore consumed GPIOs in PM sequence

Save and restore during PM suspend/resume sequences the state of the
consumed GPIOs.

Consumers are expected to get their GPIOs using

drivers: stm32_gpio: save/restore consumed GPIOs in PM sequence

Save and restore during PM suspend/resume sequences the state of the
consumed GPIOs.

Consumers are expected to get their GPIOs using the DT resources hence
register a PM handle when the GPIO is requested (stm32_gpio_get_dt()) so
that the dependency order established during drivers initialization is
satisfied during PM suspend and resume sequences. PM handle is
unregistered when consumer releases the GPIO which requires the handles
to be referenced in a list so that we can find it back.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: add stm32mp25x support

Add support for stm32mp25x platforms by adding RIF support to the driver.
GPIO banks are RIF-aware peripherals, meaning that they are responsible
for sett

drivers: stm32_gpio: add stm32mp25x support

Add support for stm32mp25x platforms by adding RIF support to the driver.
GPIO banks are RIF-aware peripherals, meaning that they are responsible
for setting their own RIF configuration.

While there, remove the use of set_bank_gpio_non_secure() as it is of no
use since a pin not configured as secured in the device tree will already
result being non-secure.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: use default PRNG init if RNG is disabled in the DT

In case RNG peripheral is not enabled in device tree, fallback to the
default RNG initialization implementation.

Signed-off-by

drivers: stm32_rng: use default PRNG init if RNG is disabled in the DT

In case RNG peripheral is not enabled in device tree, fallback to the
default RNG initialization implementation.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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driver: crypto: hisilicon: add montgomery algorithm

add operation of X25519 and X448 algorithm, including alloc_keypair,
gen_keypar and shared_secret

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Ac

driver: crypto: hisilicon: add montgomery algorithm

add operation of X25519 and X448 algorithm, including alloc_keypair,
gen_keypar and shared_secret

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_remoteproc: Add remote processor memories cleanup function

This patch introduces a new function stm32_rproc_clean_up_memories() to
clean up the memory regions used by the remote proce

drivers: stm32_remoteproc: Add remote processor memories cleanup function

This patch introduces a new function stm32_rproc_clean_up_memories() to
clean up the memory regions used by the remote processor.
The function iterates over each memory region, maps it, clears the memory
by setting it to zero, and then unmaps it.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: drivers: riscv_zkr_rng: limit seed reading time

If the attempts to read SEED exceed 1 second for 16-bit
randomness, we consider it a failure.

Also, move seed CSR field encodings to the header

core: drivers: riscv_zkr_rng: limit seed reading time

If the attempts to read SEED exceed 1 second for 16-bit
randomness, we consider it a failure.

Also, move seed CSR field encodings to the header file.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_rif: add stm32_rif_access_violation_action()

This function should be used by peripherals capable on raising
access violation interrupts (SERC, IAC). The behavior of the platform
on su

drivers: stm32_rif: add stm32_rif_access_violation_action()

This function should be used by peripherals capable on raising
access violation interrupts (SERC, IAC). The behavior of the platform
on such event is platform-specific. Therefore, its definition must be
done at platform level.

Also add CFG_STM32_PANIC_ON_IAC_EVENT and CFG_STM32_PANIC_ON_SERC_EVENT
to choose if the platform should panic upon receiving an IAC or a
SERC event.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: add stm32 SERC support

Add stm32 SERC driver support. The SERC driver collects accesses to
target peripherals that are either shutdown (computing clock off),
or under reset. Upon

drivers: firewall: add stm32 SERC support

Add stm32 SERC driver support. The SERC driver collects accesses to
target peripherals that are either shutdown (computing clock off),
or under reset. Upon such event, the platform panics as it is an
undesired event.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: add stm32 IAC support

Add stm32 IAC driver support. The IAC (illegal access controller)
centralizes the detection of RIF-related illegal accesses.

Signed-off-by: Gatien Chevallie

drivers: firewall: add stm32 IAC support

Add stm32 IAC driver support. The IAC (illegal access controller)
centralizes the detection of RIF-related illegal accesses.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: scmi-msg: fix clock rates description remaining count

Fix value of remaining clocks to describe on SCMI clock protocol
message CLOCK_DESCRIBE_RATES that does not take into account the
numbe

drivers: scmi-msg: fix clock rates description remaining count

Fix value of remaining clocks to describe on SCMI clock protocol
message CLOCK_DESCRIBE_RATES that does not take into account the
number of returned clock in the response.

Fixes: 90252e2a52c7 ("drivers: scmi-msg: clock adapts to output buffer size")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: scmi-msg: correct voltage domain protocol version

Fix the version ID of the implemented SCMI voltage domain protocol that
is v2.0 (ID 0x20000), not v3.0 (ID 0x30000).

Fixes: 006d89b8f49f (

drivers: scmi-msg: correct voltage domain protocol version

Fix the version ID of the implemented SCMI voltage domain protocol that
is v2.0 (ID 0x20000), not v3.0 (ID 0x30000).

Fixes: 006d89b8f49f ("drivers: scmi-msg: add SCMI Voltage Domain protocol")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values.

drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values. This change allows to better fit the sole consumer of this
API function that is the SCMI server implementation. SCMI specification
states that discrete clock rates list shall follow this order.

Update at91_cpu_opp clock driver to ensure it satisfy this constraint.
The SAM platforms that embed this driver (sama7g5) already satisfy this
constraints but only at its DTS level. This change ensures the driver
will always.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: crypto: hisilicon: add authenc algorithm

Add authenc algorithm for hisilicon SEC driver

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

drivers: pm: sam: specify suspend/resume hint based on suspend level

The regulators that are used with the sama5d2 platforms can enter
different levels of low power mode. In order to be able to act

drivers: pm: sam: specify suspend/resume hint based on suspend level

The regulators that are used with the sama5d2 platforms can enter
different levels of low power mode. In order to be able to act
accordingly, pass this information through suspend/resume hint.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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driver: crypto: hisilicon: replace free() and memzero() by free_wipe()

replace free() and memzero() by free_wipe()

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.f

driver: crypto: hisilicon: replace free() and memzero() by free_wipe()

replace free() and memzero() by free_wipe()

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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driver: crypto: hisilicon: delete msg->result which is not used

delete msg->result which is not used

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linar

driver: crypto: hisilicon: delete msg->result which is not used

delete msg->result which is not used

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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