1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2024, STMicroelectronics 4 */ 5 6 #include <drivers/firewall.h> 7 #include <drivers/stm32_rif.h> 8 #include <drivers/stm32_shared_io.h> 9 #include <drivers/stm32mp_dt_bindings.h> 10 #include <io.h> 11 #include <kernel/boot.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <kernel/panic.h> 15 #include <kernel/pm.h> 16 #include <libfdt.h> 17 #include <mm/core_memprot.h> 18 #include <tee_api_defines.h> 19 #include <trace.h> 20 #include <util.h> 21 22 /* RIFSC offset register */ 23 #define _RIFSC_RISC_SECCFGR0 U(0x10) 24 #define _RIFSC_RISC_PRIVCFGR0 U(0x30) 25 #define _RIFSC_RISC_RCFGLOCKR0 U(0x50) 26 #define _RIFSC_RISC_PER0_CIDCFGR U(0x100) 27 #define _RIFSC_RISC_PER0_SEMCR U(0x104) 28 #define _RIFSC_RIMC_CR U(0xC00) 29 #define _RIFSC_RIMC_ATTR0 U(0xC10) 30 31 #define _RIFSC_HWCFGR3 U(0xFE8) 32 #define _RIFSC_HWCFGR2 U(0xFEC) 33 #define _RIFSC_HWCFGR1 U(0xFF0) 34 #define _RIFSC_VERR U(0xFF4) 35 36 /* RIFSC_HWCFGR2 register fields */ 37 #define _RIFSC_HWCFGR2_CFG1_MASK GENMASK_32(15, 0) 38 #define _RIFSC_HWCFGR2_CFG1_SHIFT U(0) 39 #define _RIFSC_HWCFGR2_CFG2_MASK GENMASK_32(23, 16) 40 #define _RIFSC_HWCFGR2_CFG2_SHIFT U(16) 41 #define _RIFSC_HWCFGR2_CFG3_MASK GENMASK_32(31, 24) 42 #define _RIFSC_HWCFGR2_CFG3_SHIFT U(24) 43 44 /* RIFSC_HWCFGR1 register fields */ 45 #define _RIFSC_HWCFGR1_CFG1_MASK GENMASK_32(3, 0) 46 #define _RIFSC_HWCFGR1_CFG1_SHIFT U(0) 47 #define _RIFSC_HWCFGR1_CFG2_MASK GENMASK_32(7, 4) 48 #define _RIFSC_HWCFGR1_CFG2_SHIFT U(4) 49 #define _RIFSC_HWCFGR1_CFG3_MASK GENMASK_32(11, 8) 50 #define _RIFSC_HWCFGR1_CFG3_SHIFT U(8) 51 #define _RIFSC_HWCFGR1_CFG4_MASK GENMASK_32(15, 12) 52 #define _RIFSC_HWCFGR1_CFG4_SHIFT U(12) 53 #define _RIFSC_HWCFGR1_CFG5_MASK GENMASK_32(19, 16) 54 #define _RIFSC_HWCFGR1_CFG5_SHIFT U(16) 55 #define _RIFSC_HWCFGR1_CFG6_MASK GENMASK_32(23, 20) 56 #define _RIFSC_HWCFGR1_CFG6_SHIFT U(20) 57 58 /* 59 * RISC_CR register fields 60 */ 61 #define _RIFSC_RISC_CR_GLOCK BIT(0) 62 63 /* 64 * RIMC_CR register fields 65 */ 66 #define _RIFSC_RIMC_CR_GLOCK BIT(0) 67 #define _RIFSC_RIMC_CR_TDCID_MASK GENMASK_32(6, 4) 68 69 /* RIFSC_VERR register fields */ 70 #define _RIFSC_VERR_MINREV_MASK GENMASK_32(3, 0) 71 #define _RIFSC_VERR_MINREV_SHIFT U(0) 72 #define _RIFSC_VERR_MAJREV_MASK GENMASK_32(7, 4) 73 #define _RIFSC_VERR_MAJREV_SHIFT U(4) 74 75 /* Periph id per register */ 76 #define _PERIPH_IDS_PER_REG U(32) 77 #define _OFFSET_PERX_CIDCFGR U(0x8) 78 79 #define RIFSC_RISC_CIDCFGR_CFEN_MASK BIT(0) 80 #define RIFSC_RISC_CIDCFGR_CFEN_SHIFT U(0) 81 #define RIFSC_RISC_CIDCFGR_SEM_EN_MASK BIT(1) 82 #define RIFSC_RISC_CIDCFGR_SEM_EN_SHIFT U(1) 83 #define RIFSC_RISC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 84 #define RIFSC_RISC_CIDCFGR_SCID_SHIFT U(4) 85 #define RIFSC_RISC_CIDCFGR_LOCK_MASK BIT(10) 86 #define RIFSC_RISC_CIDCFGR_LOCK_SHIFT U(10) 87 #define RIFSC_RISC_CIDCFGR_SEML_MASK GENMASK_32(23, 16) 88 #define RIFSC_RISC_CIDCFGR_SEML_SHIFT U(16) 89 90 #define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CIDCFGR_CFEN_MASK | \ 91 RIFSC_RISC_CIDCFGR_SEM_EN_MASK | \ 92 RIFSC_RISC_CIDCFGR_SCID_MASK | \ 93 RIFSC_RISC_CIDCFGR_SCID_SHIFT) 94 95 #define RIFSC_RISC_PERx_CID_SHIFT U(0) 96 97 #define RIFSC_RIMC_MODE_MASK BIT(2) 98 #define RIFSC_RIMC_MCID_MASK GENMASK_32(6, 4) 99 #define RIFSC_RIMC_MSEC_MASK BIT(8) 100 #define RIFSC_RIMC_MPRIV_MASK BIT(9) 101 #define RIFSC_RIMC_M_ID_MASK GENMASK_32(23, 16) 102 103 #define RIFSC_RIMC_ATTRx_MASK (RIFSC_RIMC_MODE_MASK | \ 104 RIFSC_RIMC_MCID_MASK | \ 105 RIFSC_RIMC_MSEC_MASK | \ 106 RIFSC_RIMC_MPRIV_MASK) 107 108 /* max entries */ 109 #define MAX_RIMU U(16) 110 #define MAX_RISUP U(128) 111 112 #define _RIF_FLD_GET(field, value) (((uint32_t)(value) & \ 113 (field ## _MASK)) >>\ 114 (field ## _SHIFT)) 115 116 struct risup_cfg { 117 uint32_t cid_attr; 118 uint32_t id; 119 bool sec; 120 bool priv; 121 bool lock; 122 bool pm_sem; 123 }; 124 125 struct rimu_cfg { 126 uint32_t id; 127 uint32_t attr; 128 }; 129 130 struct rifsc_driver_data { 131 bool rif_en; 132 bool sec_en; 133 bool priv_en; 134 uint8_t nb_rimu; 135 uint8_t nb_risup; 136 uint8_t nb_risal; 137 uint8_t version; 138 }; 139 140 struct rifsc_platdata { 141 uintptr_t base; 142 struct rifsc_driver_data *drv_data; 143 struct risup_cfg *risup; 144 unsigned int nrisup; 145 struct rimu_cfg *rimu; 146 unsigned int nrimu; 147 bool is_tdcid; 148 }; 149 150 /* There is only 1 instance of the RIFSC subsystem */ 151 static struct rifsc_driver_data rifsc_drvdata; 152 static struct rifsc_platdata rifsc_pdata; 153 154 static void stm32_rifsc_get_driverdata(struct rifsc_platdata *pdata) 155 { 156 uint32_t regval = 0; 157 158 regval = io_read32(pdata->base + _RIFSC_HWCFGR1); 159 rifsc_drvdata.rif_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG1, regval) != 0; 160 rifsc_drvdata.sec_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG2, regval) != 0; 161 rifsc_drvdata.priv_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG3, regval) != 0; 162 163 regval = io_read32(pdata->base + _RIFSC_HWCFGR2); 164 rifsc_drvdata.nb_risup = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG1, regval); 165 rifsc_drvdata.nb_rimu = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG2, regval); 166 rifsc_drvdata.nb_risal = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG3, regval); 167 168 pdata->drv_data = &rifsc_drvdata; 169 170 rifsc_drvdata.version = io_read8(pdata->base + _RIFSC_VERR); 171 172 DMSG("RIFSC version %"PRIu32".%"PRIu32, 173 _RIF_FLD_GET(_RIFSC_VERR_MAJREV, rifsc_drvdata.version), 174 _RIF_FLD_GET(_RIFSC_VERR_MINREV, rifsc_drvdata.version)); 175 176 DMSG("HW cap: enabled[rif:sec:priv]:[%s:%s:%s] nb[risup|rimu|risal]:[%"PRIu8",%"PRIu8",%"PRIu8"]", 177 rifsc_drvdata.rif_en ? "true" : "false", 178 rifsc_drvdata.sec_en ? "true" : "false", 179 rifsc_drvdata.priv_en ? "true" : "false", 180 rifsc_drvdata.nb_risup, 181 rifsc_drvdata.nb_rimu, 182 rifsc_drvdata.nb_risal); 183 } 184 185 static TEE_Result stm32_rifsc_glock_config(const void *fdt, int node, 186 struct rifsc_platdata *pdata) 187 { 188 const fdt32_t *cuint = NULL; 189 uint32_t glock_conf = 0; 190 int len = 0; 191 192 cuint = fdt_getprop(fdt, node, "st,glocked", &len); 193 if (!cuint) { 194 DMSG("No global lock on RIF configuration"); 195 return TEE_SUCCESS; 196 } 197 assert(len == sizeof(uint32_t)); 198 199 glock_conf = fdt32_to_cpu(*cuint); 200 201 if (glock_conf & RIFSC_RIMU_GLOCK) { 202 DMSG("Setting global lock on RIMU configuration"); 203 204 io_setbits32(pdata->base + _RIFSC_RIMC_CR, 205 _RIFSC_RIMC_CR_GLOCK); 206 207 if (!(io_read32(pdata->base + _RIFSC_RIMC_CR) & 208 _RIFSC_RIMC_CR_GLOCK)) 209 return TEE_ERROR_ACCESS_DENIED; 210 } 211 212 if (glock_conf & RIFSC_RISUP_GLOCK) { 213 DMSG("Setting global lock on RISUP configuration"); 214 215 io_setbits32(pdata->base, _RIFSC_RISC_CR_GLOCK); 216 217 if (!(io_read32(pdata->base) & _RIFSC_RISC_CR_GLOCK)) 218 return TEE_ERROR_ACCESS_DENIED; 219 } 220 221 return TEE_SUCCESS; 222 } 223 224 static TEE_Result stm32_rifsc_dt_conf_risup(const void *fdt, int node, 225 struct rifsc_platdata *pdata) 226 { 227 const fdt32_t *conf_list = NULL; 228 unsigned int i = 0; 229 int len = 0; 230 231 conf_list = fdt_getprop(fdt, node, "st,protreg", &len); 232 if (!conf_list) { 233 DMSG("No RISUP configuration in DT"); 234 return TEE_ERROR_ITEM_NOT_FOUND; 235 } 236 assert(!(len % sizeof(uint32_t))); 237 238 pdata->nrisup = len / sizeof(uint32_t); 239 pdata->risup = calloc(pdata->nrisup, sizeof(*pdata->risup)); 240 if (!pdata->risup) 241 return TEE_ERROR_OUT_OF_MEMORY; 242 243 for (i = 0; i < pdata->nrisup; i++) { 244 uint32_t value = fdt32_to_cpu(conf_list[i]); 245 struct risup_cfg *risup = pdata->risup + i; 246 247 risup->id = _RIF_FLD_GET(RIF_PER_ID, value); 248 risup->sec = _RIF_FLD_GET(RIF_SEC, value) != 0; 249 risup->priv = _RIF_FLD_GET(RIF_PRIV, value) != 0; 250 risup->lock = _RIF_FLD_GET(RIF_LOCK, value) != 0; 251 risup->cid_attr = _RIF_FLD_GET(RIF_PERx_CID, value); 252 } 253 254 return TEE_SUCCESS; 255 } 256 257 static TEE_Result stm32_rifsc_dt_conf_rimu(const void *fdt, int node, 258 struct rifsc_platdata *pdata) 259 { 260 const fdt32_t *conf_list = NULL; 261 unsigned int i = 0; 262 int len = 0; 263 264 conf_list = fdt_getprop(fdt, node, "st,rimu", &len); 265 if (!conf_list) { 266 DMSG("No RIMU configuration in DT"); 267 return TEE_ERROR_ITEM_NOT_FOUND; 268 } 269 assert(!(len % sizeof(uint32_t))); 270 271 pdata->nrimu = len / sizeof(uint32_t); 272 pdata->rimu = calloc(pdata->nrimu, sizeof(*pdata->rimu)); 273 if (!pdata->rimu) 274 return TEE_ERROR_OUT_OF_MEMORY; 275 276 for (i = 0; i < pdata->nrimu; i++) { 277 uint32_t value = fdt32_to_cpu(*conf_list); 278 struct rimu_cfg *rimu = pdata->rimu + i; 279 280 rimu->id = _RIF_FLD_GET(RIMUPROT_RIMC_M_ID, value) - 281 RIMU_ID_OFFSET; 282 rimu->attr = _RIF_FLD_GET(RIMUPROT_RIMC_ATTRx, value); 283 } 284 285 return TEE_SUCCESS; 286 } 287 288 static TEE_Result stm32_rifsc_parse_fdt(const void *fdt, int node, 289 struct rifsc_platdata *pdata) 290 { 291 TEE_Result res = TEE_ERROR_GENERIC; 292 struct io_pa_va base = { }; 293 size_t reg_size = 0; 294 295 base.pa = fdt_reg_base_address(fdt, node); 296 if (base.pa == DT_INFO_INVALID_REG) 297 return TEE_ERROR_BAD_PARAMETERS; 298 299 reg_size = fdt_reg_size(fdt, node); 300 if (reg_size == DT_INFO_INVALID_REG_SIZE) 301 return TEE_ERROR_BAD_PARAMETERS; 302 303 pdata->base = io_pa_or_va_secure(&base, reg_size); 304 305 res = stm32_rifsc_check_tdcid(&rifsc_pdata.is_tdcid); 306 if (res) 307 panic(); 308 309 res = stm32_rifsc_dt_conf_risup(fdt, node, pdata); 310 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 311 return res; 312 313 if (rifsc_pdata.is_tdcid) { 314 res = stm32_rifsc_dt_conf_rimu(fdt, node, pdata); 315 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 316 return res; 317 } 318 319 return stm32_rifsc_dt_conf_rimu(fdt, node, pdata); 320 } 321 322 static TEE_Result stm32_risup_cfg(struct rifsc_platdata *pdata, 323 struct risup_cfg *risup) 324 { 325 uintptr_t offset = sizeof(uint32_t) * (risup->id / _PERIPH_IDS_PER_REG); 326 uintptr_t cidcfgr_offset = _OFFSET_PERX_CIDCFGR * risup->id; 327 struct rifsc_driver_data *drv_data = pdata->drv_data; 328 uint32_t shift = risup->id % _PERIPH_IDS_PER_REG; 329 TEE_Result res = TEE_ERROR_GENERIC; 330 331 if (!risup || risup->id >= drv_data->nb_risup) 332 return TEE_ERROR_BAD_PARAMETERS; 333 334 if (drv_data->sec_en) 335 io_clrsetbits32_stm32shregs(pdata->base + _RIFSC_RISC_SECCFGR0 + 336 offset, BIT(shift), 337 SHIFT_U32(risup->sec, shift)); 338 339 if (drv_data->priv_en) 340 io_clrsetbits32_stm32shregs(pdata->base + 341 _RIFSC_RISC_PRIVCFGR0 + offset, 342 BIT(shift), 343 SHIFT_U32(risup->priv, shift)); 344 345 if (rifsc_pdata.is_tdcid) { 346 if (drv_data->rif_en) 347 io_write32(pdata->base + _RIFSC_RISC_PER0_CIDCFGR + 348 cidcfgr_offset, risup->cid_attr); 349 350 /* Lock configuration for this RISUP */ 351 if (risup->lock) { 352 DMSG("Locking RIF conf for peripheral ID: %"PRIu32, 353 risup->id); 354 io_setbits32_stm32shregs(pdata->base + 355 _RIFSC_RISC_RCFGLOCKR0 + 356 offset, BIT(shift)); 357 } 358 } 359 360 /* Take semaphore if the resource is in semaphore mode and secured */ 361 if (stm32_rif_semaphore_enabled_and_ok(risup->cid_attr, RIF_CID1)) { 362 if (!(io_read32(pdata->base + _RIFSC_RISC_SECCFGR0 + offset) & 363 BIT(shift))) { 364 res = 365 stm32_rif_release_semaphore(pdata->base + 366 _RIFSC_RISC_PER0_SEMCR + 367 cidcfgr_offset, 368 MAX_CID_SUPPORTED); 369 if (res) { 370 EMSG("Couldn't release semaphore for resource %"PRIu32, 371 risup->id); 372 return TEE_ERROR_ACCESS_DENIED; 373 } 374 } else { 375 res = 376 stm32_rif_acquire_semaphore(pdata->base + 377 _RIFSC_RISC_PER0_SEMCR + 378 cidcfgr_offset, 379 MAX_CID_SUPPORTED); 380 if (res) { 381 EMSG("Couldn't acquire semaphore for resource %"PRIu32, 382 risup->id); 383 return TEE_ERROR_ACCESS_DENIED; 384 } 385 } 386 } 387 388 return TEE_SUCCESS; 389 } 390 391 static TEE_Result stm32_risup_setup(struct rifsc_platdata *pdata) 392 { 393 struct rifsc_driver_data *drv_data = pdata->drv_data; 394 TEE_Result res = TEE_ERROR_GENERIC; 395 unsigned int i = 0; 396 397 for (i = 0; i < pdata->nrisup && i < drv_data->nb_risup; i++) { 398 struct risup_cfg *risup = pdata->risup + i; 399 400 res = stm32_risup_cfg(pdata, risup); 401 if (res) { 402 EMSG("risup cfg(%d/%d) error", i + 1, pdata->nrisup); 403 return res; 404 } 405 } 406 407 return TEE_SUCCESS; 408 } 409 410 static TEE_Result stm32_rimu_cfg(struct rifsc_platdata *pdata, 411 struct rimu_cfg *rimu) 412 { 413 uintptr_t offset = _RIFSC_RIMC_ATTR0 + (sizeof(uint32_t) * rimu->id); 414 struct rifsc_driver_data *drv_data = pdata->drv_data; 415 416 if (!rimu || rimu->id >= drv_data->nb_rimu) 417 return TEE_ERROR_BAD_PARAMETERS; 418 419 if (drv_data->rif_en) 420 io_write32(pdata->base + offset, rimu->attr); 421 422 return TEE_SUCCESS; 423 } 424 425 static TEE_Result stm32_rimu_setup(struct rifsc_platdata *pdata) 426 { 427 struct rifsc_driver_data *drv_data = pdata->drv_data; 428 TEE_Result res = TEE_ERROR_GENERIC; 429 unsigned int i = 0; 430 431 for (i = 0; i < pdata->nrimu && i < drv_data->nb_rimu; i++) { 432 struct rimu_cfg *rimu = pdata->rimu + i; 433 434 res = stm32_rimu_cfg(pdata, rimu); 435 if (res) { 436 EMSG("rimu cfg(%d/%d) error", i + 1, pdata->nrimu); 437 return res; 438 } 439 } 440 441 return TEE_SUCCESS; 442 } 443 444 static TEE_Result stm32_rifsc_check_access(struct firewall_query *firewall) 445 { 446 uintptr_t rifsc_base = rifsc_pdata.base; 447 unsigned int cid_reg_offset = 0; 448 unsigned int periph_offset = 0; 449 unsigned int resource_id = 0; 450 uint32_t cid_to_check = 0; 451 unsigned int reg_id = 0; 452 bool priv_check = true; 453 bool sec_check = true; 454 uint32_t privcfgr = 0; 455 uint32_t seccfgr = 0; 456 uint32_t cidcfgr = 0; 457 458 assert(rifsc_base); 459 460 if (!firewall || firewall->arg_count != 1) 461 return TEE_ERROR_BAD_PARAMETERS; 462 463 /* 464 * Peripheral configuration, we assume the configuration is as 465 * follows: 466 * firewall->args[0]: RIF configuration to check 467 */ 468 resource_id = firewall->args[0] & RIF_PER_ID_MASK; 469 if (resource_id >= RIMU_ID_OFFSET) 470 return TEE_SUCCESS; 471 472 reg_id = resource_id / _PERIPH_IDS_PER_REG; 473 periph_offset = resource_id % _PERIPH_IDS_PER_REG; 474 cid_reg_offset = _OFFSET_PERX_CIDCFGR * resource_id; 475 cidcfgr = io_read32(rifsc_base + _RIFSC_RISC_PER0_CIDCFGR + 476 cid_reg_offset); 477 seccfgr = io_read32(rifsc_base + _RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); 478 privcfgr = io_read32(rifsc_base + _RIFSC_RISC_PRIVCFGR0 + 0x4 * reg_id); 479 sec_check = (BIT(RIF_SEC_SHIFT) & firewall->args[0]) != 0; 480 priv_check = (BIT(RIF_PRIV_SHIFT) & firewall->args[0]) != 0; 481 cid_to_check = (firewall->args[0] & RIF_SCID_MASK) >> RIF_SCID_SHIFT; 482 483 if (!sec_check && seccfgr & BIT(periph_offset)) 484 return TEE_ERROR_ACCESS_DENIED; 485 486 if (!priv_check && (privcfgr & BIT(periph_offset))) 487 return TEE_ERROR_ACCESS_DENIED; 488 489 if (!(cidcfgr & _CIDCFGR_CFEN)) 490 return TEE_SUCCESS; 491 492 if ((cidcfgr & _CIDCFGR_SEMEN && 493 !stm32_rif_semaphore_enabled_and_ok(cidcfgr, cid_to_check)) || 494 (!(cidcfgr & _CIDCFGR_SEMEN) && 495 !stm32_rif_scid_ok(cidcfgr, RIFSC_RISC_CIDCFGR_SCID_MASK, 496 cid_to_check))) 497 return TEE_ERROR_BAD_PARAMETERS; 498 499 return TEE_SUCCESS; 500 } 501 502 static TEE_Result stm32_rifsc_acquire_access(struct firewall_query *firewall) 503 { 504 uintptr_t rifsc_base = rifsc_pdata.base; 505 unsigned int cid_reg_offset = 0; 506 unsigned int resource_id = 0; 507 uint32_t cidcfgr = 0; 508 509 assert(rifsc_base); 510 511 if (!firewall || !firewall->arg_count) 512 return TEE_ERROR_BAD_PARAMETERS; 513 514 /* 515 * Peripheral configuration, we assume the configuration is as 516 * follows: 517 * firewall->args[0]: Firewall ID of the resource to acquire 518 */ 519 resource_id = firewall->args[0] & RIF_PER_ID_MASK; 520 if (resource_id >= RIMU_ID_OFFSET) 521 return TEE_SUCCESS; 522 523 cid_reg_offset = _OFFSET_PERX_CIDCFGR * resource_id; 524 cidcfgr = io_read32(rifsc_base + _RIFSC_RISC_PER0_CIDCFGR + 525 cid_reg_offset); 526 527 /* Only check CID attributes */ 528 if (!(cidcfgr & _CIDCFGR_CFEN)) 529 return TEE_SUCCESS; 530 531 if (cidcfgr & _CIDCFGR_SEMEN) { 532 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 533 return TEE_ERROR_BAD_PARAMETERS; 534 535 /* Take the semaphore, static CID is irrelevant here */ 536 return stm32_rif_acquire_semaphore(rifsc_base + 537 _RIFSC_RISC_PER0_SEMCR + 538 cid_reg_offset, 539 MAX_CID_SUPPORTED); 540 } 541 542 if (!stm32_rif_scid_ok(cidcfgr, RIFSC_RISC_CIDCFGR_SCID_MASK, RIF_CID1)) 543 return TEE_ERROR_ACCESS_DENIED; 544 545 return TEE_SUCCESS; 546 } 547 548 static TEE_Result stm32_rifsc_set_config(struct firewall_query *firewall) 549 { 550 struct rimu_cfg rimu = { }; 551 unsigned int id = 0; 552 uint32_t conf = 0; 553 554 if (!firewall || firewall->arg_count != 1) 555 return TEE_ERROR_BAD_PARAMETERS; 556 557 /* 558 * Peripheral configuration, we assume the configuration is as 559 * follows: 560 * firewall->args[0]: RIF configuration to set 561 */ 562 id = firewall->args[0] & RIF_PER_ID_MASK; 563 conf = firewall->args[0]; 564 565 if (id < RIMU_ID_OFFSET) { 566 struct risup_cfg risup = { }; 567 uint32_t cidcfgr = 0; 568 569 risup.id = id; 570 risup.sec = (BIT(RIF_SEC_SHIFT) & conf) != 0; 571 risup.priv = (BIT(RIF_PRIV_SHIFT) & conf) != 0; 572 risup.lock = (BIT(RIF_LOCK_SHIFT) & conf) != 0; 573 risup.cid_attr = _RIF_FLD_GET(RIF_PERx_CID, conf); 574 575 if (!rifsc_pdata.is_tdcid) { 576 cidcfgr = io_read32(rifsc_pdata.base + 577 _OFFSET_PERX_CIDCFGR * risup.id + 578 _RIFSC_RISC_PER0_CIDCFGR); 579 580 if (cidcfgr != risup.cid_attr) 581 return TEE_ERROR_BAD_PARAMETERS; 582 } 583 584 DMSG("Setting config for peripheral: %u, %s, %s, cid attr: %#"PRIx32", %s", 585 id, risup.sec ? "Secure" : "Non secure", 586 risup.priv ? "Privileged" : "Non privileged", 587 risup.cid_attr, risup.lock ? "Locked" : "Unlocked"); 588 589 return stm32_risup_cfg(&rifsc_pdata, &risup); 590 } 591 592 if (!rifsc_pdata.is_tdcid) 593 return TEE_ERROR_ACCESS_DENIED; 594 595 rimu.id = _RIF_FLD_GET(RIMUPROT_RIMC_M_ID, conf) - RIMU_ID_OFFSET; 596 rimu.attr = _RIF_FLD_GET(RIMUPROT_RIMC_ATTRx, conf); 597 598 return stm32_rimu_cfg(&rifsc_pdata, &rimu); 599 } 600 601 static void stm32_rifsc_release_access(struct firewall_query *firewall) 602 { 603 uintptr_t rifsc_base = rifsc_pdata.base; 604 uint32_t cidcfgr = 0; 605 uint32_t id = 0; 606 607 assert(rifsc_base && firewall && firewall->arg_count); 608 609 id = firewall->args[0]; 610 611 if (id >= RIMU_ID_OFFSET) 612 return; 613 614 cidcfgr = io_read32(rifsc_base + _RIFSC_RISC_PER0_CIDCFGR + 615 _OFFSET_PERX_CIDCFGR * id); 616 617 /* Only thing possible is to release a semaphore taken by OP-TEE CID */ 618 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 619 if (stm32_rif_release_semaphore(rifsc_base + 620 _RIFSC_RISC_PER0_SEMCR + 621 id * _OFFSET_PERX_CIDCFGR, 622 MAX_CID_SUPPORTED)) 623 panic("Could not release the RIF semaphore"); 624 } 625 626 static TEE_Result stm32_rifsc_sem_pm_suspend(void) 627 { 628 unsigned int i = 0; 629 630 for (i = 0; i < rifsc_pdata.nrisup && i < rifsc_drvdata.nb_risup; i++) { 631 uint32_t semcfgr = io_read32(rifsc_pdata.base + 632 _RIFSC_RISC_PER0_SEMCR + 633 _OFFSET_PERX_CIDCFGR * i); 634 struct risup_cfg *risup = rifsc_pdata.risup + i; 635 636 /* Save semaphores that were taken by the CID1 */ 637 risup->pm_sem = semcfgr & _SEMCR_MUTEX && 638 ((semcfgr & _SEMCR_SEMCID_MASK) >> 639 _SEMCR_SEMCID_SHIFT) == RIF_CID1; 640 641 FMSG("RIF semaphore %s for ID: %"PRIu32, 642 risup->pm_sem ? "SAVED" : "NOT SAVED", risup->id); 643 } 644 645 return TEE_SUCCESS; 646 } 647 648 static TEE_Result stm32_rifsc_sem_pm_resume(void) 649 { 650 TEE_Result res = TEE_ERROR_GENERIC; 651 unsigned int i = 0; 652 653 for (i = 0; i < rifsc_pdata.nrisup && i < rifsc_drvdata.nb_risup; i++) { 654 struct risup_cfg *risup = rifsc_pdata.risup + i; 655 uintptr_t cidcfgr_offset = _OFFSET_PERX_CIDCFGR * risup->id; 656 uintptr_t offset = sizeof(uint32_t) * 657 (risup->id / _PERIPH_IDS_PER_REG); 658 uintptr_t perih_offset = risup->id % _PERIPH_IDS_PER_REG; 659 uint32_t seccgfr = io_read32(rifsc_pdata.base + 660 _RIFSC_RISC_SECCFGR0 + offset); 661 uint32_t privcgfr = io_read32(rifsc_pdata.base + 662 _RIFSC_RISC_PRIVCFGR0 + offset); 663 uint32_t lockcfgr = io_read32(rifsc_pdata.base + 664 _RIFSC_RISC_RCFGLOCKR0 + offset); 665 666 /* Update RISUPs fields */ 667 risup->cid_attr = io_read32(rifsc_pdata.base + 668 _RIFSC_RISC_PER0_CIDCFGR + 669 cidcfgr_offset); 670 risup->sec = (seccgfr & BIT(perih_offset)) != 0; 671 risup->priv = (privcgfr & BIT(perih_offset)) != 0; 672 risup->lock = (lockcfgr & BIT(perih_offset)) != 0; 673 674 /* Acquire available appropriate semaphores */ 675 if (!stm32_rif_semaphore_enabled_and_ok(risup->cid_attr, 676 RIF_CID1) || 677 !risup->pm_sem) 678 continue; 679 680 res = stm32_rif_acquire_semaphore(rifsc_pdata.base + 681 _RIFSC_RISC_PER0_SEMCR + 682 cidcfgr_offset, 683 MAX_CID_SUPPORTED); 684 if (res) { 685 EMSG("Could not acquire semaphore for resource %"PRIu32, 686 risup->id); 687 return TEE_ERROR_ACCESS_DENIED; 688 } 689 } 690 691 return TEE_SUCCESS; 692 } 693 694 static TEE_Result 695 stm32_rifsc_sem_pm(enum pm_op op, unsigned int pm_hint, 696 const struct pm_callback_handle *pm_handle __unused) 697 { 698 TEE_Result res = TEE_ERROR_GENERIC; 699 700 if (pm_hint != PM_HINT_CONTEXT_STATE) 701 return TEE_SUCCESS; 702 703 if (op == PM_OP_RESUME) 704 res = stm32_rifsc_sem_pm_resume(); 705 else 706 res = stm32_rifsc_sem_pm_suspend(); 707 708 return res; 709 } 710 711 TEE_Result stm32_rifsc_check_tdcid(bool *tdcid_state) 712 { 713 if (!rifsc_pdata.base) 714 return TEE_ERROR_DEFER_DRIVER_INIT; 715 716 if (((io_read32(rifsc_pdata.base + _RIFSC_RIMC_CR) & 717 _RIFSC_RIMC_CR_TDCID_MASK)) == (RIF_CID1 << SCID_SHIFT)) 718 *tdcid_state = true; 719 else 720 *tdcid_state = false; 721 722 return TEE_SUCCESS; 723 } 724 725 static const struct firewall_controller_ops firewall_ops = { 726 .set_conf = stm32_rifsc_set_config, 727 .check_access = stm32_rifsc_check_access, 728 .acquire_access = stm32_rifsc_acquire_access, 729 .release_access = stm32_rifsc_release_access, 730 }; 731 732 static TEE_Result stm32_rifsc_probe(const void *fdt, int node, 733 const void *compat_data __unused) 734 { 735 struct firewall_controller *controller = NULL; 736 TEE_Result res = TEE_ERROR_GENERIC; 737 738 res = stm32_rifsc_parse_fdt(fdt, node, &rifsc_pdata); 739 if (res) { 740 EMSG("Could not parse RIFSC node, res = %#"PRIx32, res); 741 panic(); 742 } 743 744 if (!rifsc_pdata.drv_data) 745 stm32_rifsc_get_driverdata(&rifsc_pdata); 746 747 res = stm32_risup_setup(&rifsc_pdata); 748 if (res) { 749 EMSG("Could not setup RISUPs, res = %#"PRIx32, res); 750 panic(); 751 } 752 753 if (rifsc_pdata.is_tdcid) { 754 res = stm32_rimu_setup(&rifsc_pdata); 755 if (res) { 756 EMSG("Could not setup RIMUs, res = %#"PRIx32, res); 757 panic(); 758 } 759 } 760 761 res = stm32_rifsc_glock_config(fdt, node, &rifsc_pdata); 762 if (res) 763 panic("Couldn't lock RIFSC configuration"); 764 765 controller = calloc(1, sizeof(*controller)); 766 if (!controller) 767 panic(); 768 769 controller->name = "RIFSC"; 770 controller->priv = &rifsc_pdata; 771 controller->ops = &firewall_ops; 772 773 res = firewall_dt_controller_register(fdt, node, controller); 774 if (res) 775 panic(); 776 777 res = firewall_dt_probe_bus(fdt, node, controller); 778 if (res) 779 panic(); 780 781 register_pm_core_service_cb(stm32_rifsc_sem_pm, NULL, 782 "stm32-rifsc-semaphores"); 783 784 return TEE_SUCCESS; 785 } 786 787 static const struct dt_device_match rifsc_match_table[] = { 788 { .compatible = "st,stm32mp25-rifsc" }, 789 { } 790 }; 791 792 DEFINE_DT_DRIVER(rifsc_dt_driver) = { 793 .name = "stm32-rifsc", 794 .match_table = rifsc_match_table, 795 .probe = stm32_rifsc_probe, 796 }; 797