1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2024, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/gpio.h> 13 #include <drivers/pinctrl.h> 14 #include <drivers/stm32_gpio.h> 15 #include <drivers/stm32_rif.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <io.h> 18 #include <kernel/dt.h> 19 #include <kernel/boot.h> 20 #include <kernel/panic.h> 21 #include <kernel/spinlock.h> 22 #include <libfdt.h> 23 #include <mm/core_memprot.h> 24 #include <stdbool.h> 25 #include <stdint.h> 26 #include <stm32_util.h> 27 #include <sys/queue.h> 28 #include <trace.h> 29 #include <util.h> 30 31 #ifndef CFG_DRIVERS_GPIO 32 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 33 #endif 34 35 #define GPIO_PIN_MAX 15 36 37 #define GPIO_MODER_OFFSET U(0x00) 38 #define GPIO_OTYPER_OFFSET U(0x04) 39 #define GPIO_OSPEEDR_OFFSET U(0x08) 40 #define GPIO_PUPDR_OFFSET U(0x0c) 41 #define GPIO_IDR_OFFSET U(0x10) 42 #define GPIO_ODR_OFFSET U(0x14) 43 #define GPIO_BSRR_OFFSET U(0x18) 44 #define GPIO_AFRL_OFFSET U(0x20) 45 #define GPIO_AFRH_OFFSET U(0x24) 46 #define GPIO_SECR_OFFSET U(0x30) 47 #define GPIO_PRIVCFGR_OFFSET U(0x34) 48 #define GPIO_RCFGLOCKR_OFFSET U(0x38) 49 #define GPIO_CIDCFGR(x) (U(0x50) + U(0x8) * (x)) 50 #define GPIO_SEMCR(x) (U(0x54) + U(0x8) * (x)) 51 52 #define GPIO_ALT_LOWER_LIMIT U(0x8) 53 54 /* 55 * CIDCFGR register bitfields 56 */ 57 #define GPIO_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 58 #define GPIO_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 59 #define GPIO_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | _CIDCFGR_SEMEN | \ 60 GPIO_CIDCFGR_SCID_MASK | \ 61 GPIO_CIDCFGR_SEMWL_MASK) 62 63 /* 64 * PRIVCFGR register bitfields 65 */ 66 #define GPIO_PRIVCFGR_MASK GENMASK_32(15, 0) 67 68 /* 69 * SECCFGR register bitfields 70 */ 71 #define GPIO_SECCFGR_MASK GENMASK_32(15, 0) 72 73 /* 74 * RCFGLOCKR register bitfields 75 */ 76 #define GPIO_RCFGLOCKR_MASK GENMASK_32(15, 0) 77 78 /* 79 * SEMCR register bitfields 80 */ 81 #define GPIO_SEMCR_SCID_M GENMASK_32(6, 4) 82 83 #define GPIO_MODE_MASK GENMASK_32(1, 0) 84 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 85 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 86 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 87 88 #define DT_GPIO_BANK_SHIFT U(12) 89 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 90 #define DT_GPIO_PIN_SHIFT U(8) 91 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 92 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 93 94 #define DT_GPIO_BANK_NAME0 "GPIOA" 95 96 #define GPIO_MODE_INPUT U(0x0) 97 #define GPIO_MODE_OUTPUT U(0x1) 98 #define GPIO_MODE_ALTERNATE U(0x2) 99 #define GPIO_MODE_ANALOG U(0x3) 100 101 #define GPIO_OTYPE_PUSH_PULL U(0x0) 102 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 103 104 #define GPIO_OSPEED_LOW U(0x0) 105 #define GPIO_OSPEED_MEDIUM U(0x1) 106 #define GPIO_OSPEED_HIGH U(0x2) 107 #define GPIO_OSPEED_VERY_HIGH U(0x3) 108 109 #define GPIO_PUPD_NO_PULL U(0x0) 110 #define GPIO_PUPD_PULL_UP U(0x1) 111 #define GPIO_PUPD_PULL_DOWN U(0x2) 112 113 #define GPIO_OD_LEVEL_LOW U(0x0) 114 #define GPIO_OD_LEVEL_HIGH U(0x1) 115 116 #define GPIO_MAX_CID_SUPPORTED U(3) 117 118 /* 119 * GPIO configuration description structured as single 16bit word 120 * for efficient save/restore when GPIO pin suspends or resumes. 121 * 122 * @mode: One of GPIO_MODE_* 123 * @otype: One of GPIO_OTYPE_* 124 * @ospeed: One of GPIO_OSPEED_* 125 * @pupd: One of GPIO_PUPD_* 126 * @od: One of GPIO_OD_* 127 * @af: Alternate function numerical ID between 0 and 15 128 */ 129 struct gpio_cfg { 130 uint16_t mode: 2; 131 uint16_t otype: 1; 132 uint16_t ospeed: 2; 133 uint16_t pupd: 2; 134 uint16_t od: 1; 135 uint16_t af: 4; 136 }; 137 138 /* 139 * Description of a pin and its muxing 140 * 141 * @bank: GPIO bank identifier as assigned by the platform 142 * @pin: Pin number in the GPIO bank 143 * @cfg: Pin configuration 144 */ 145 struct stm32_pinctrl { 146 uint8_t bank; 147 uint8_t pin; 148 struct gpio_cfg cfg; 149 }; 150 151 /* 152 * struct stm32_pinctrl_array - Array of pins in a pin control state 153 * @count: Number of cells in @pinctrl 154 * @pinctrl: Pin control configuration 155 */ 156 struct stm32_pinctrl_array { 157 size_t count; 158 struct stm32_pinctrl pinctrl[]; 159 }; 160 161 /** 162 * struct stm32_gpio_bank - GPIO bank instance 163 * 164 * @base: base address of the GPIO controller registers. 165 * @clock: clock identifier. 166 * @gpio_chip: GPIO chip reference for that GPIO bank 167 * @ngpios: number of GPIOs. 168 * @bank_id: Id of the bank. 169 * @lock: lock protecting the GPIO bank access. 170 * @rif_cfg: RIF configuration data 171 * @seccfgr: non-RIF bank secure configuration data 172 * @sec_support: True if bank supports pin security protection, else false 173 * @ready: True if configuration is applied, else false 174 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID 175 * @link: Link in bank list 176 */ 177 struct stm32_gpio_bank { 178 vaddr_t base; 179 struct clk *clock; 180 struct gpio_chip gpio_chip; 181 unsigned int ngpios; 182 unsigned int bank_id; 183 unsigned int lock; 184 struct rif_conf_data *rif_cfg; 185 uint32_t seccfgr; 186 bool sec_support; 187 bool ready; 188 bool is_tdcid; 189 STAILQ_ENTRY(stm32_gpio_bank) link; 190 }; 191 192 /** 193 * Compatibility information of supported banks 194 * 195 * @gpioz: True if bank is a GPIOZ bank 196 * @secure_control: Identify GPIO security bank capability. 197 * @secure_extended: Identify RIF presence. 198 */ 199 struct bank_compat { 200 bool gpioz; 201 bool secure_control; 202 bool secure_extended; 203 }; 204 205 static unsigned int gpio_lock; 206 207 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 208 STAILQ_HEAD_INITIALIZER(bank_list); 209 210 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 211 212 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 213 { 214 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 215 } 216 217 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 218 unsigned int gpio_pin) 219 { 220 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 221 enum gpio_level level = GPIO_LEVEL_HIGH; 222 unsigned int reg_offset = 0; 223 unsigned int mode = 0; 224 225 assert(gpio_pin < bank->ngpios); 226 227 if (clk_enable(bank->clock)) 228 panic(); 229 230 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 231 GPIO_MODE_MASK; 232 233 switch (mode) { 234 case GPIO_MODE_INPUT: 235 reg_offset = GPIO_IDR_OFFSET; 236 break; 237 case GPIO_MODE_OUTPUT: 238 reg_offset = GPIO_ODR_OFFSET; 239 break; 240 default: 241 panic(); 242 } 243 244 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 245 level = GPIO_LEVEL_HIGH; 246 else 247 level = GPIO_LEVEL_LOW; 248 249 clk_disable(bank->clock); 250 251 return level; 252 } 253 254 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 255 enum gpio_level level) 256 { 257 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 258 259 assert(gpio_pin < bank->ngpios); 260 261 if (clk_enable(bank->clock)) 262 panic(); 263 264 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 265 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 266 267 if (level == GPIO_LEVEL_HIGH) 268 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 269 else 270 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 271 272 clk_disable(bank->clock); 273 } 274 275 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 276 unsigned int gpio_pin) 277 { 278 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 279 uint32_t mode = 0; 280 281 assert(gpio_pin < bank->ngpios); 282 283 if (clk_enable(bank->clock)) 284 panic(); 285 286 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 287 GPIO_MODE_MASK; 288 289 clk_disable(bank->clock); 290 291 switch (mode) { 292 case GPIO_MODE_INPUT: 293 return GPIO_DIR_IN; 294 case GPIO_MODE_OUTPUT: 295 return GPIO_DIR_OUT; 296 default: 297 panic(); 298 } 299 } 300 301 static void stm32_gpio_set_direction(struct gpio_chip *chip, 302 unsigned int gpio_pin, 303 enum gpio_dir direction) 304 { 305 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 306 uint32_t exceptions = 0; 307 uint32_t mode = 0; 308 309 assert(gpio_pin < bank->ngpios); 310 311 if (direction == GPIO_DIR_IN) 312 mode = GPIO_MODE_INPUT; 313 else 314 mode = GPIO_MODE_OUTPUT; 315 316 if (clk_enable(bank->clock)) 317 panic(); 318 exceptions = cpu_spin_lock_xsave(&gpio_lock); 319 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 320 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 321 SHIFT_U32(mode, gpio_pin << 1)); 322 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 323 clk_disable(bank->clock); 324 } 325 326 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 327 struct gpio *gpio) 328 { 329 assert(is_stm32_gpio_chip(chip)); 330 free(gpio); 331 } 332 333 static const struct gpio_ops stm32_gpio_ops = { 334 .get_direction = stm32_gpio_get_direction, 335 .set_direction = stm32_gpio_set_direction, 336 .get_value = stm32_gpio_get_level, 337 .set_value = stm32_gpio_set_level, 338 .put = stm32_gpio_put_gpio, 339 }; 340 341 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 342 { 343 return chip && chip->ops == &stm32_gpio_ops; 344 } 345 346 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 347 { 348 struct stm32_gpio_bank *bank = NULL; 349 350 STAILQ_FOREACH(bank, &bank_list, link) 351 if (bank_id == bank->bank_id) 352 return bank; 353 354 panic(); 355 } 356 357 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 358 static void __maybe_unused get_gpio_cfg(uint32_t bank_id, uint32_t pin, 359 struct gpio_cfg *cfg) 360 { 361 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 362 363 if (clk_enable(bank->clock)) 364 panic(); 365 366 /* 367 * Save GPIO configuration bits spread over the few bank registers. 368 * 1bit fields are accessed at bit position being the pin index. 369 * 2bit fields are accessed at bit position being twice the pin index. 370 * 4bit fields are accessed at bit position being fourth the pin index 371 * but accessed from 2 32bit registers at incremental addresses. 372 */ 373 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 374 GPIO_MODE_MASK; 375 376 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 377 378 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 379 (pin << 1)) & GPIO_OSPEED_MASK; 380 381 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 382 GPIO_PUPD_PULL_MASK; 383 384 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 385 386 if (pin < GPIO_ALT_LOWER_LIMIT) 387 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 388 (pin << 2)) & GPIO_ALTERNATE_MASK; 389 else 390 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 391 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 392 GPIO_ALTERNATE_MASK; 393 394 clk_disable(bank->clock); 395 } 396 397 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 398 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 399 { 400 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 401 uint32_t exceptions = 0; 402 403 if (clk_enable(bank->clock)) 404 panic(); 405 exceptions = cpu_spin_lock_xsave(&gpio_lock); 406 407 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 408 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 409 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 410 SHIFT_U32(cfg->mode, pin << 1)); 411 412 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 413 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 414 SHIFT_U32(cfg->otype, pin)); 415 416 /* Load GPIO Output Speed confguration, 2bit value */ 417 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 418 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 419 SHIFT_U32(cfg->ospeed, pin << 1)); 420 421 /* Load GPIO pull configuration, 2bit value */ 422 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 423 SHIFT_U32(cfg->pupd, pin << 1)); 424 425 /* Load pin mux Alternate Function configuration, 4bit value */ 426 if (pin < GPIO_ALT_LOWER_LIMIT) { 427 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 428 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 429 SHIFT_U32(cfg->af, pin << 2)); 430 } else { 431 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 432 433 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 434 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 435 SHIFT_U32(cfg->af, shift)); 436 } 437 438 /* Load GPIO Output direction confuguration, 1bit */ 439 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 440 441 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 442 clk_disable(bank->clock); 443 } 444 445 /* Count pins described in the DT node and get related data if possible */ 446 static int get_pinctrl_from_fdt(const void *fdt, int node, 447 struct stm32_pinctrl *pinctrl, size_t count) 448 { 449 const fdt32_t *cuint = NULL; 450 const fdt32_t *slewrate = NULL; 451 int len = 0; 452 uint32_t i = 0; 453 uint32_t speed = GPIO_OSPEED_LOW; 454 uint32_t pull = GPIO_PUPD_NO_PULL; 455 size_t found = 0; 456 457 cuint = fdt_getprop(fdt, node, "pinmux", &len); 458 if (!cuint) 459 return -FDT_ERR_NOTFOUND; 460 461 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 462 if (slewrate) 463 speed = fdt32_to_cpu(*slewrate); 464 465 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 466 pull = GPIO_PUPD_PULL_UP; 467 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 468 pull = GPIO_PUPD_PULL_DOWN; 469 470 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 471 uint32_t pincfg = 0; 472 uint32_t bank = 0; 473 uint32_t pin = 0; 474 uint32_t mode = 0; 475 uint32_t alternate = 0; 476 uint32_t odata = 0; 477 bool opendrain = false; 478 479 pincfg = fdt32_to_cpu(*cuint); 480 cuint++; 481 482 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 483 484 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 485 486 mode = pincfg & DT_GPIO_MODE_MASK; 487 488 switch (mode) { 489 case 0: 490 mode = GPIO_MODE_INPUT; 491 break; 492 case 1: 493 case 2: 494 case 3: 495 case 4: 496 case 5: 497 case 6: 498 case 7: 499 case 8: 500 case 9: 501 case 10: 502 case 11: 503 case 12: 504 case 13: 505 case 14: 506 case 15: 507 case 16: 508 alternate = mode - 1U; 509 mode = GPIO_MODE_ALTERNATE; 510 break; 511 case 17: 512 mode = GPIO_MODE_ANALOG; 513 break; 514 default: 515 mode = GPIO_MODE_OUTPUT; 516 break; 517 } 518 519 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 520 opendrain = true; 521 522 if (fdt_getprop(fdt, node, "output-high", NULL) && 523 mode == GPIO_MODE_INPUT) { 524 mode = GPIO_MODE_OUTPUT; 525 odata = 1; 526 } 527 528 if (fdt_getprop(fdt, node, "output-low", NULL) && 529 mode == GPIO_MODE_INPUT) { 530 mode = GPIO_MODE_OUTPUT; 531 odata = 0; 532 } 533 534 if (found < count) { 535 struct stm32_pinctrl *ref = &pinctrl[found]; 536 537 ref->bank = (uint8_t)bank; 538 ref->pin = (uint8_t)pin; 539 ref->cfg.mode = mode; 540 if (opendrain) 541 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 542 else 543 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 544 ref->cfg.ospeed = speed; 545 ref->cfg.pupd = pull; 546 ref->cfg.od = odata; 547 ref->cfg.af = alternate; 548 } 549 550 found++; 551 } 552 553 return (int)found; 554 } 555 556 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 557 struct gpio **out_gpio) 558 { 559 TEE_Result res = TEE_ERROR_GENERIC; 560 struct stm32_gpio_bank *bank = data; 561 struct gpio *gpio = NULL; 562 unsigned int shift_1b = 0; 563 unsigned int shift_2b = 0; 564 uint32_t exceptions = 0; 565 uint32_t otype = 0; 566 uint32_t pupd = 0; 567 uint32_t mode = 0; 568 569 res = gpio_dt_alloc_pin(pargs, &gpio); 570 if (res) 571 return res; 572 573 if (gpio->pin >= bank->ngpios) { 574 DMSG("Invalid GPIO reference"); 575 free(gpio); 576 return TEE_ERROR_GENERIC; 577 } 578 579 shift_1b = gpio->pin; 580 shift_2b = SHIFT_U32(gpio->pin, 1); 581 582 if (gpio->dt_flags & GPIO_PULL_UP) 583 pupd = GPIO_PUPD_PULL_UP; 584 else if (gpio->dt_flags & GPIO_PULL_DOWN) 585 pupd = GPIO_PUPD_PULL_DOWN; 586 else 587 pupd = GPIO_PUPD_NO_PULL; 588 589 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 590 otype = GPIO_OTYPE_OPEN_DRAIN; 591 else 592 otype = GPIO_OTYPE_PUSH_PULL; 593 594 if (clk_enable(bank->clock)) 595 panic(); 596 exceptions = cpu_spin_lock_xsave(&gpio_lock); 597 598 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 599 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 600 SHIFT_U32(mode, shift_2b)); 601 602 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 603 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 604 SHIFT_U32(otype, shift_1b)); 605 606 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 607 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 608 SHIFT_U32(pupd, shift_2b)); 609 610 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 611 clk_disable(bank->clock); 612 613 gpio->chip = &bank->gpio_chip; 614 615 *out_gpio = gpio; 616 617 return TEE_SUCCESS; 618 } 619 620 /* Get bank ID from bank node property st,bank-name or panic on failure */ 621 static unsigned int dt_get_bank_id(const void *fdt, int node) 622 { 623 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 624 const fdt32_t *cuint = NULL; 625 int len = 0; 626 627 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 628 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 629 if (!cuint || (len != dt_name_len + 1)) 630 panic("Missing/wrong st,bank-name property"); 631 632 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 633 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 634 panic("Wrong st,bank-name property"); 635 636 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 637 } 638 639 /* 640 * Return whether or not the GPIO bank related to a DT node is already 641 * registered in the GPIO bank link. 642 */ 643 static bool bank_is_registered(const void *fdt, int node) 644 { 645 unsigned int bank_id = dt_get_bank_id(fdt, node); 646 struct stm32_gpio_bank *bank = NULL; 647 648 STAILQ_FOREACH(bank, &bank_list, link) 649 if (bank->bank_id == bank_id) 650 return true; 651 652 return false; 653 } 654 655 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank) 656 { 657 TEE_Result res = TEE_ERROR_GENERIC; 658 uint32_t cidcfgr = 0; 659 unsigned int i = 0; 660 661 if (!bank->rif_cfg) 662 return TEE_SUCCESS; 663 664 if (clk_enable(bank->clock)) 665 panic(); 666 667 for (i = 0; i < bank->ngpios; i++) { 668 if (!(BIT(i) & bank->rif_cfg->access_mask[0])) 669 continue; 670 671 /* 672 * When TDCID, OP-TEE should be the one to set the CID filtering 673 * configuration. Clearing previous configuration prevents 674 * undesired events during the only legitimate configuration. 675 */ 676 if (bank->is_tdcid) 677 io_clrbits32(bank->base + GPIO_CIDCFGR(i), 678 GPIO_CIDCFGR_CONF_MASK); 679 680 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); 681 682 /* Check if the controller is in semaphore mode */ 683 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 684 continue; 685 686 /* If not TDCID, we want to acquire semaphores assigned to us */ 687 res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(i), 688 GPIO_MAX_CID_SUPPORTED); 689 if (res) { 690 EMSG("Could not acquire semaphore for pin %c%u", 691 'A' + bank->bank_id, i); 692 goto out; 693 } 694 } 695 696 /* Security and privilege RIF configuration */ 697 io_clrsetbits32(bank->base + GPIO_PRIVCFGR_OFFSET, GPIO_PRIVCFGR_MASK, 698 bank->rif_cfg->priv_conf[0]); 699 io_clrsetbits32(bank->base + GPIO_SECR_OFFSET, GPIO_SECCFGR_MASK, 700 bank->rif_cfg->sec_conf[0]); 701 702 if (!bank->is_tdcid) { 703 res = TEE_SUCCESS; 704 goto out; 705 } 706 707 for (i = 0; i < bank->ngpios; i++) { 708 if (!(BIT(i) & bank->rif_cfg->access_mask[0])) 709 continue; 710 711 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i), 712 GPIO_CIDCFGR_CONF_MASK, 713 bank->rif_cfg->cid_confs[i]); 714 715 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); 716 717 /* 718 * Take semaphore if the resource is in semaphore mode 719 * and secured. 720 */ 721 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) || 722 !(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) { 723 res = stm32_rif_release_semaphore(bank->base + 724 GPIO_SEMCR(i), 725 GPIO_MAX_CID_SUPPORTED); 726 if (res) { 727 EMSG("Could not release semaphore for pin %c%u", 728 'A' + bank->bank_id, i); 729 goto out; 730 } 731 } else { 732 res = stm32_rif_acquire_semaphore(bank->base + 733 GPIO_SEMCR(i), 734 GPIO_MAX_CID_SUPPORTED); 735 if (res) { 736 EMSG("Could not acquire semaphore for pin %c%u", 737 'A' + bank->bank_id, i); 738 goto out; 739 } 740 } 741 } 742 743 /* 744 * Lock RIF configuration if configured. This cannot be undone until 745 * next reset. 746 */ 747 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET, 748 bank->rif_cfg->lock_conf[0]); 749 750 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 751 /* Check that RIF config are applied, panic otherwise */ 752 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) & 753 bank->rif_cfg->access_mask[0]) != 754 bank->rif_cfg->priv_conf[0]) { 755 EMSG("GPIO bank%c priv conf is incorrect", 756 'A' + bank->bank_id); 757 panic(); 758 } 759 760 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & 761 bank->rif_cfg->access_mask[0]) != 762 bank->rif_cfg->sec_conf[0]) { 763 EMSG("GPIO bank %c sec conf is incorrect", 764 'A' + bank->bank_id); 765 panic(); 766 } 767 } 768 769 res = TEE_SUCCESS; 770 out: 771 clk_disable(bank->clock); 772 773 return res; 774 } 775 776 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank, 777 const void *fdt, int node) 778 { 779 unsigned int i = 0; 780 unsigned int nb_rif_conf = 0; 781 int lenp = 0; 782 const fdt32_t *cuint = NULL; 783 784 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 785 if (!cuint) { 786 DMSG("No RIF configuration available"); 787 return; 788 } 789 790 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg)); 791 if (!bank->rif_cfg) 792 panic(); 793 794 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t)); 795 if (!bank->rif_cfg->sec_conf) 796 panic(); 797 798 nb_rif_conf = (unsigned int)(lenp / sizeof(uint32_t)); 799 assert(nb_rif_conf <= bank->ngpios); 800 801 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t)); 802 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t)); 803 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t)); 804 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t)); 805 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask || 806 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf) 807 panic("Missing memory capacity for GPIOS RIF configuration"); 808 809 for (i = 0; i < nb_rif_conf; i++) 810 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg, 811 GPIO_MAX_CID_SUPPORTED, bank->ngpios); 812 } 813 814 /* Get GPIO bank information from the DT */ 815 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 816 const void *compat_data, 817 int range_offset, 818 struct stm32_gpio_bank **out_bank) 819 { 820 const struct bank_compat *compat = compat_data; 821 TEE_Result res = TEE_ERROR_GENERIC; 822 struct stm32_gpio_bank *bank = NULL; 823 const fdt32_t *cuint = NULL; 824 struct io_pa_va pa_va = { }; 825 struct clk *clk = NULL; 826 size_t blen = 0; 827 paddr_t pa = 0; 828 int len = 0; 829 int i = 0; 830 831 assert(out_bank); 832 833 /* Probe deferrable devices first */ 834 res = clk_dt_get_by_index(fdt, node, 0, &clk); 835 if (res) 836 return res; 837 838 bank = calloc(1, sizeof(*bank)); 839 if (!bank) 840 return TEE_ERROR_OUT_OF_MEMORY; 841 842 if (compat->secure_extended) { 843 res = stm32_rifsc_check_tdcid(&bank->is_tdcid); 844 if (res) { 845 free(bank); 846 return res; 847 } 848 } 849 850 /* 851 * Do not rely *only* on the "reg" property to get the address, 852 * but consider also the "ranges" translation property 853 */ 854 pa = fdt_reg_base_address(fdt, node); 855 if (pa == DT_INFO_INVALID_REG) 856 panic("missing reg property"); 857 858 pa_va.pa = pa + range_offset; 859 860 blen = fdt_reg_size(fdt, node); 861 if (blen == DT_INFO_INVALID_REG_SIZE) 862 panic("missing reg size property"); 863 864 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 865 bank->bank_id = dt_get_bank_id(fdt, node); 866 bank->clock = clk; 867 bank->gpio_chip.ops = &stm32_gpio_ops; 868 bank->sec_support = compat->secure_control; 869 870 /* Parse gpio-ranges with its 4 parameters */ 871 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 872 len /= sizeof(*cuint); 873 if (len % 4) 874 panic("wrong gpio-ranges syntax"); 875 876 /* Get the last defined gpio line (offset + nb of pins) */ 877 for (i = 0; i < len / 4; i++) { 878 bank->ngpios = MAX(bank->ngpios, 879 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 880 fdt32_to_cpu(*(cuint + 3)))); 881 cuint += 4; 882 } 883 884 if (compat->secure_extended) { 885 /* RIF configuration */ 886 bank->base = io_pa_or_va_secure(&pa_va, blen); 887 888 stm32_parse_gpio_rif_conf(bank, fdt, node); 889 } else if (bank->sec_support) { 890 /* Secure configuration */ 891 bank->base = io_pa_or_va_secure(&pa_va, blen); 892 cuint = fdt_getprop(fdt, node, "st,protreg", NULL); 893 if (cuint) 894 bank->seccfgr = fdt32_to_cpu(*cuint); 895 else 896 DMSG("GPIO bank %c assigned to non-secure", 897 bank->bank_id + 'A'); 898 } else { 899 bank->base = io_pa_or_va_nsec(&pa_va, blen); 900 } 901 902 if (compat->gpioz) 903 stm32mp_register_gpioz_pin_count(bank->ngpios); 904 905 *out_bank = bank; 906 907 return TEE_SUCCESS; 908 } 909 910 /* Parse a pinctrl node to register the GPIO banks it describes */ 911 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 912 const void *compat_data) 913 { 914 TEE_Result res = TEE_SUCCESS; 915 const fdt32_t *cuint = NULL; 916 int range_offs = 0; 917 int b_node = 0; 918 int len = 0; 919 920 /* Read the ranges property (for regs memory translation) */ 921 cuint = fdt_getprop(fdt, node, "ranges", &len); 922 if (!cuint) 923 panic("missing ranges property"); 924 925 len /= sizeof(*cuint); 926 if (len == 3) 927 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 928 929 fdt_for_each_subnode(b_node, fdt, node) { 930 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 931 if (cuint) { 932 /* 933 * We found a property "gpio-controller" in the node: 934 * the node is a GPIO bank description, add it to the 935 * bank list. 936 */ 937 struct stm32_gpio_bank *bank = NULL; 938 939 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 940 bank_is_registered(fdt, b_node)) 941 continue; 942 943 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 944 range_offs, &bank); 945 if (res) 946 return res; 947 948 /* Registering a provider should not defer probe */ 949 res = gpio_register_provider(fdt, b_node, 950 stm32_gpio_get_dt, bank); 951 if (res) 952 panic(); 953 954 STAILQ_INSERT_TAIL(&bank_list, bank, link); 955 } else { 956 if (len != -FDT_ERR_NOTFOUND) 957 panic(); 958 } 959 } 960 961 return TEE_SUCCESS; 962 } 963 964 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 965 bool secure) 966 { 967 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 968 uint32_t exceptions = 0; 969 970 if (clk_enable(bank->clock)) 971 panic(); 972 exceptions = cpu_spin_lock_xsave(&gpio_lock); 973 974 if (secure) 975 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 976 else 977 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 978 979 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 980 clk_disable(bank->clock); 981 } 982 983 #ifdef CFG_DRIVERS_PINCTRL 984 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 985 { 986 struct stm32_pinctrl_array *ref = conf->priv; 987 struct stm32_pinctrl *p = ref->pinctrl; 988 size_t pin_count = ref->count; 989 size_t n = 0; 990 991 for (n = 0; n < pin_count; n++) 992 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 993 994 return TEE_SUCCESS; 995 } 996 997 static void stm32_pinctrl_conf_free(struct pinconf *conf) 998 { 999 free(conf); 1000 } 1001 1002 static const struct pinctrl_ops stm32_pinctrl_ops = { 1003 .conf_apply = stm32_pinctrl_conf_apply, 1004 .conf_free = stm32_pinctrl_conf_free, 1005 }; 1006 1007 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 1008 1009 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 1010 unsigned int *bank, unsigned int *pin, 1011 unsigned int *count) 1012 { 1013 size_t conf_index = 0; 1014 size_t pin_count = 0; 1015 size_t n = 0; 1016 1017 assert(count); 1018 if (!pinctrl) 1019 goto out; 1020 1021 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1022 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1023 struct stm32_pinctrl_array *ref = pinconf->priv; 1024 1025 /* Consider only the stm32_gpio pins */ 1026 if (pinconf->ops != &stm32_pinctrl_ops) 1027 continue; 1028 1029 if (bank || pin) { 1030 for (n = 0; n < ref->count; n++) { 1031 if (bank && pin_count < *count) 1032 bank[pin_count] = ref->pinctrl[n].bank; 1033 if (pin && pin_count < *count) 1034 pin[pin_count] = ref->pinctrl[n].pin; 1035 pin_count++; 1036 } 1037 } else { 1038 pin_count += ref->count; 1039 } 1040 } 1041 1042 out: 1043 *count = pin_count; 1044 } 1045 1046 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 1047 { 1048 size_t conf_index = 0; 1049 1050 if (!pinctrl) 1051 return; 1052 1053 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1054 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1055 struct stm32_pinctrl_array *ref = pinconf->priv; 1056 struct stm32_pinctrl *pc = NULL; 1057 size_t n = 0; 1058 1059 for (n = 0; n < ref->count; n++) { 1060 if (pinconf->ops != &stm32_pinctrl_ops) 1061 continue; 1062 1063 pc = ref->pinctrl + n; 1064 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 1065 } 1066 } 1067 } 1068 1069 /* Allocate and return a pinctrl configuration from a DT reference */ 1070 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 1071 void *data __unused, 1072 struct pinconf **out_pinconf) 1073 { 1074 struct conf { 1075 struct pinconf pinconf; 1076 struct stm32_pinctrl_array array_ref; 1077 } *loc_conf = NULL; 1078 struct stm32_pinctrl *pinctrl = NULL; 1079 struct pinconf *pinconf = NULL; 1080 const void *fdt = NULL; 1081 size_t pin_count = 0; 1082 int pinctrl_node = 0; 1083 int pinmux_node = 0; 1084 int count = 0; 1085 1086 pinctrl_node = pargs->phandle_node; 1087 fdt = pargs->fdt; 1088 assert(fdt && pinctrl_node); 1089 1090 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1091 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 1092 pin_count += (size_t)count / sizeof(uint32_t); 1093 else if (count != -FDT_ERR_NOTFOUND) 1094 panic(); 1095 } 1096 1097 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 1098 if (!loc_conf) 1099 return TEE_ERROR_OUT_OF_MEMORY; 1100 1101 pinconf = &loc_conf->pinconf; 1102 pinconf->ops = &stm32_pinctrl_ops; 1103 pinconf->priv = &loc_conf->array_ref; 1104 1105 loc_conf->array_ref.count = pin_count; 1106 pinctrl = loc_conf->array_ref.pinctrl; 1107 1108 count = 0; 1109 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1110 int found = 0; 1111 1112 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 1113 pin_count - count); 1114 if (found <= 0 && found > ((int)pin_count - count)) { 1115 /* We can't recover from an error here so let's panic */ 1116 panic(); 1117 } 1118 1119 count += found; 1120 } 1121 1122 *out_pinconf = pinconf; 1123 1124 return TEE_SUCCESS; 1125 } 1126 #endif /*CFG_DRIVERS_PINCTRL*/ 1127 1128 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank) 1129 { 1130 if (bank->sec_support) { 1131 clk_enable(bank->clock); 1132 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); 1133 clk_disable(bank->clock); 1134 } 1135 } 1136 1137 /* 1138 * Several pinctrl nodes can be probed. Their bank will be put in the unique 1139 * bank_list. To avoid multiple configuration set for a bank when looping 1140 * over each bank in the bank list, ready is set to true when a bank is 1141 * configured. Therefore, during other bank probes, the configuration won't 1142 * be set again. 1143 */ 1144 static TEE_Result apply_sec_cfg(void) 1145 { 1146 TEE_Result res = TEE_ERROR_GENERIC; 1147 struct stm32_gpio_bank *bank = NULL; 1148 1149 STAILQ_FOREACH(bank, &bank_list, link) { 1150 if (bank->ready) 1151 continue; 1152 1153 if (bank->rif_cfg) { 1154 res = apply_rif_config(bank); 1155 if (res) { 1156 EMSG("Failed to set GPIO bank %c RIF config", 1157 'A' + bank->bank_id); 1158 STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank, 1159 link); 1160 return res; 1161 } 1162 } else { 1163 stm32_gpio_set_conf_sec(bank); 1164 } 1165 1166 bank->ready = true; 1167 } 1168 1169 return TEE_SUCCESS; 1170 } 1171 1172 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 1173 const void *compat_data) 1174 { 1175 TEE_Result res = TEE_ERROR_GENERIC; 1176 1177 /* Register GPIO banks described in this pin control node */ 1178 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 1179 if (res) 1180 return res; 1181 1182 if (STAILQ_EMPTY(&bank_list)) 1183 DMSG("no gpio bank for that driver"); 1184 else if (apply_sec_cfg()) 1185 panic(); 1186 1187 #ifdef CFG_DRIVERS_PINCTRL 1188 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 1189 (void *)compat_data); 1190 if (res) 1191 panic(); 1192 #endif 1193 1194 return TEE_SUCCESS; 1195 } 1196 1197 static const struct dt_device_match stm32_pinctrl_match_table[] = { 1198 { 1199 .compatible = "st,stm32mp135-pinctrl", 1200 .compat_data = &(struct bank_compat){ 1201 .secure_control = true, 1202 .secure_extended = false, 1203 }, 1204 }, 1205 { 1206 .compatible = "st,stm32mp157-pinctrl", 1207 .compat_data = &(struct bank_compat){ 1208 .secure_control = false, 1209 .secure_extended = false, 1210 }, 1211 }, 1212 { 1213 .compatible = "st,stm32mp157-z-pinctrl", 1214 .compat_data = &(struct bank_compat){ 1215 .gpioz = true, 1216 .secure_control = true, 1217 .secure_extended = false, 1218 }, 1219 }, 1220 { 1221 .compatible = "st,stm32mp257-pinctrl", 1222 .compat_data = &(struct bank_compat){ 1223 .secure_control = true, 1224 .secure_extended = true, 1225 }, 1226 }, 1227 { 1228 .compatible = "st,stm32mp257-z-pinctrl", 1229 .compat_data = &(struct bank_compat){ 1230 .gpioz = true, 1231 .secure_control = true, 1232 .secure_extended = true, 1233 }, 1234 }, 1235 { } 1236 }; 1237 1238 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 1239 .name = "stm32_gpio-pinctrl", 1240 .type = DT_DRIVER_PINCTRL, 1241 .match_table = stm32_pinctrl_match_table, 1242 .probe = stm32_pinctrl_probe, 1243 }; 1244