xref: /optee_os/core/arch/arm/dts/stm32mp251.dtsi (revision 471cec144fa3a994156d0bb96aad35e9a9f8ca9d) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/st,stm32mp25-rcc.h>
8#include <dt-bindings/firewall/stm32mp25-rifsc.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/reset/st,stm32mp25-rcc.h>
11
12/ {
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			compatible = "arm,cortex-a35";
22			device_type = "cpu";
23			reg = <0>;
24			enable-method = "psci";
25		};
26	};
27
28	psci {
29		compatible = "arm,psci-1.0";
30		method = "smc";
31	};
32
33	intc: interrupt-controller@4ac00000 {
34		compatible = "arm,cortex-a7-gic";
35		#interrupt-cells = <3>;
36		interrupt-controller;
37		reg = <0x0 0x4ac10000 0x0 0x1000>,
38		      <0x0 0x4ac20000 0x0 0x2000>,
39		      <0x0 0x4ac40000 0x0 0x2000>,
40		      <0x0 0x4ac60000 0x0 0x2000>;
41		#address-cells = <1>;
42	};
43
44	clocks {
45		clk_hse: clk-hse {
46			#clock-cells = <0>;
47			compatible = "fixed-clock";
48			clock-frequency = <24000000>;
49		};
50
51		clk_hsi: clk-hsi {
52			#clock-cells = <0>;
53			compatible = "fixed-clock";
54			clock-frequency = <64000000>;
55		};
56
57		clk_lse: clk-lse {
58			#clock-cells = <0>;
59			compatible = "fixed-clock";
60			clock-frequency = <32768>;
61		};
62
63		clk_lsi: clk-lsi {
64			#clock-cells = <0>;
65			compatible = "fixed-clock";
66			clock-frequency = <32000>;
67		};
68
69		clk_msi: clk-msi {
70			#clock-cells = <0>;
71			compatible = "fixed-clock";
72			clock-frequency = <4000000>;
73		};
74
75		clk_i2sin: clk-i2sin {
76			#clock-cells = <0>;
77			compatible = "fixed-clock";
78			clock-frequency = <0>;
79		};
80
81		clk_rcbsec: clk-rcbsec {
82			#clock-cells = <0>;
83			compatible = "fixed-clock";
84			clock-frequency = <64000000>;
85		};
86	};
87
88	soc@0 {
89		compatible = "simple-bus";
90		#address-cells = <1>;
91		#size-cells = <1>;
92		interrupt-parent = <&intc>;
93		ranges = <0x0 0x0 0x0 0x80000000>;
94
95		hpdma1: dma-controller@40400000 {
96			compatible = "st,stm32-dma3";
97			reg = <0x40400000 0x1000>;
98			#dma-cells = <4>;
99			status = "disabled";
100		};
101
102		hpdma2: dma-controller@40410000 {
103			compatible = "st,stm32-dma3";
104			reg = <0x40410000 0x1000>;
105			#dma-cells = <4>;
106			status = "disabled";
107		};
108
109		hpdma3: dma-controller@40420000 {
110			compatible = "st,stm32-dma3";
111			reg = <0x40420000 0x1000>;
112			#dma-cells = <4>;
113			status = "disabled";
114		};
115
116		ipcc1: mailbox@40490000 {
117			compatible = "st,stm32mp25-ipcc";
118			reg = <0x40490000 0x400>;
119			status = "disabled";
120		};
121
122		rifsc: rifsc@42080000 {
123			compatible = "st,stm32mp25-rifsc", "simple-bus";
124			reg = <0x42080000 0x1000>;
125			#address-cells = <1>;
126			#size-cells = <1>;
127			#access-controller-cells = <1>;
128
129			usart2: serial@400e0000 {
130				compatible = "st,stm32h7-uart";
131				reg = <0x400e0000 0x400>;
132				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
133				clocks = <&rcc CK_KER_USART2>;
134				access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>;
135				status = "disabled";
136			};
137		};
138
139		iac: iac@42090000 {
140			compatible = "st,stm32mp25-iac";
141			reg = <0x42090000 0x400>;
142			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
143		};
144
145		risaf1: risaf@420a0000 {
146			compatible = "st,stm32mp25-risaf";
147			reg = <0x420a0000 0x1000>;
148			clocks = <&rcc CK_BUS_BKPSRAM>;
149			st,mem-map = <0x0 0x42000000 0x0 0x2000>;
150		};
151
152		risaf2: risaf@420b0000 {
153			compatible = "st,stm32mp25-risaf";
154			reg = <0x420b0000 0x1000>;
155			clocks = <&rcc CK_KER_OSPI1>;
156			st,mem-map = <0x0 0x60000000 0x0 0x10000000>;
157			status = "disabled";
158		};
159
160		risaf4: risaf@420d0000 {
161			compatible = "st,stm32mp25-risaf-enc";
162			reg = <0x420d0000 0x1000>;
163			clocks = <&rcc CK_BUS_RISAF4>;
164			st,mem-map = <0x0 0x80000000 0x1 0x00000000>;
165		};
166
167		risaf5: risaf@420e0000 {
168			compatible = "st,stm32mp25-risaf";
169			reg = <0x420e0000 0x1000>;
170			clocks = <&rcc CK_BUS_PCIE>;
171			st,mem-map = <0x0 0x10000000 0x0 0x10000000>;
172			status = "disabled";
173		};
174
175		serc: serc@44080000 {
176			compatible = "st,stm32mp25-serc";
177			reg = <0x44080000 0x1000>;
178			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
179			clocks = <&rcc CK_BUS_SERC>;
180		};
181
182		rcc: rcc@44200000 {
183			compatible = "st,stm32mp25-rcc", "syscon";
184			reg = <0x44200000 0x10000>;
185			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
186
187			#clock-cells = <1>;
188			#reset-cells = <1>;
189			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>,
190				 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>;
191			clock-names = "clk-hse", "clk-hsi", "clk-lse",
192				      "clk-lsi", "clk-msi", "clk-i2sin";
193
194			hsi_calibration: hsi-calibration {
195				compatible = "st,hsi-cal";
196				st,cal_hsi_dev = <31>;
197				st,cal_hsi_ref = <1953>;
198				status = "disabled";
199			};
200
201			msi_calibration: msi-calibration {
202				compatible = "st,msi-cal";
203				status = "disabled";
204			};
205		};
206
207		pinctrl: pinctrl@44240000 {
208			#address-cells = <1>;
209			#size-cells = <1>;
210			compatible = "st,stm32mp257-pinctrl";
211			ranges = <0 0x44240000 0xa0400>;
212			pins-are-numbered;
213
214			gpioa: gpio@44240000 {
215				gpio-controller;
216				#gpio-cells = <2>;
217				interrupt-controller;
218				#interrupt-cells = <2>;
219				reg = <0x0 0x400>;
220				clocks = <&rcc CK_BUS_GPIOA>;
221				st,bank-name = "GPIOA";
222				status = "disabled";
223			};
224
225			gpiob: gpio@44250000 {
226				gpio-controller;
227				#gpio-cells = <2>;
228				interrupt-controller;
229				#interrupt-cells = <2>;
230				reg = <0x10000 0x400>;
231				clocks = <&rcc CK_BUS_GPIOB>;
232				st,bank-name = "GPIOB";
233				status = "disabled";
234			};
235
236			gpioc: gpio@44260000 {
237				gpio-controller;
238				#gpio-cells = <2>;
239				interrupt-controller;
240				#interrupt-cells = <2>;
241				reg = <0x20000 0x400>;
242				clocks = <&rcc CK_BUS_GPIOC>;
243				st,bank-name = "GPIOC";
244				status = "disabled";
245			};
246
247			gpiod: gpio@44270000 {
248				gpio-controller;
249				#gpio-cells = <2>;
250				interrupt-controller;
251				#interrupt-cells = <2>;
252				reg = <0x30000 0x400>;
253				clocks = <&rcc CK_BUS_GPIOD>;
254				st,bank-name = "GPIOD";
255				status = "disabled";
256			};
257
258			gpioe: gpio@44280000 {
259				gpio-controller;
260				#gpio-cells = <2>;
261				interrupt-controller;
262				#interrupt-cells = <2>;
263				reg = <0x40000 0x400>;
264				clocks = <&rcc CK_BUS_GPIOE>;
265				st,bank-name = "GPIOE";
266				status = "disabled";
267			};
268
269			gpiof: gpio@44290000 {
270				gpio-controller;
271				#gpio-cells = <2>;
272				interrupt-controller;
273				#interrupt-cells = <2>;
274				reg = <0x50000 0x400>;
275				clocks = <&rcc CK_BUS_GPIOF>;
276				st,bank-name = "GPIOF";
277				status = "disabled";
278			};
279
280			gpiog: gpio@442a0000 {
281				gpio-controller;
282				#gpio-cells = <2>;
283				interrupt-controller;
284				#interrupt-cells = <2>;
285				reg = <0x60000 0x400>;
286				clocks = <&rcc CK_BUS_GPIOG>;
287				st,bank-name = "GPIOG";
288				status = "disabled";
289			};
290
291			gpioh: gpio@442b0000 {
292				gpio-controller;
293				#gpio-cells = <2>;
294				interrupt-controller;
295				#interrupt-cells = <2>;
296				reg = <0x70000 0x400>;
297				clocks = <&rcc CK_BUS_GPIOH>;
298				st,bank-name = "GPIOH";
299				status = "disabled";
300			};
301
302			gpioi: gpio@442c0000 {
303				gpio-controller;
304				#gpio-cells = <2>;
305				interrupt-controller;
306				#interrupt-cells = <2>;
307				reg = <0x80000 0x400>;
308				clocks = <&rcc CK_BUS_GPIOI>;
309				st,bank-name = "GPIOI";
310				status = "disabled";
311			};
312
313			gpioj: gpio@442d0000 {
314				gpio-controller;
315				#gpio-cells = <2>;
316				interrupt-controller;
317				#interrupt-cells = <2>;
318				reg = <0x90000 0x400>;
319				clocks = <&rcc CK_BUS_GPIOJ>;
320				st,bank-name = "GPIOJ";
321				status = "disabled";
322			};
323
324			gpiok: gpio@442e0000 {
325				gpio-controller;
326				#gpio-cells = <2>;
327				interrupt-controller;
328				#interrupt-cells = <2>;
329				reg = <0xa0000 0x400>;
330				clocks = <&rcc CK_BUS_GPIOK>;
331				st,bank-name = "GPIOK";
332				status = "disabled";
333			};
334		};
335
336		pinctrl_z: pinctrl-z@46200000 {
337			#address-cells = <1>;
338			#size-cells = <1>;
339			compatible = "st,stm32mp257-z-pinctrl";
340			ranges = <0 0x46200000 0x400>;
341			pins-are-numbered;
342
343			gpioz: gpio@46200000 {
344				gpio-controller;
345				#gpio-cells = <2>;
346				interrupt-controller;
347				#interrupt-cells = <2>;
348				reg = <0 0x400>;
349				clocks = <&rcc CK_BUS_GPIOZ>;
350				st,bank-name = "GPIOZ";
351				st,bank-ioport = <11>;
352				status = "disabled";
353			};
354		};
355
356		hsem: hwspinlock@46240000 {
357			compatible = "st,stm32mp25-hsem";
358			reg = <0x46240000 0x400>;
359			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
360			status = "disabled";
361		};
362
363		ipcc2: mailbox@46250000 {
364			compatible = "st,stm32mp25-ipcc";
365			reg = <0x46250000 0x400>;
366			status = "disabled";
367		};
368
369		fmc: memory-controller@48200000 {
370			#address-cells = <2>;
371			#size-cells = <1>;
372			compatible = "st,stm32mp25-fmc2-ebi";
373			reg = <0x48200000 0x400>;
374			status = "disabled";
375
376			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
377				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
378				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
379				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
380				 <4 0 0x80000000 0x10000000>; /* NAND */
381		};
382	};
383};
384