drivers: stm32_rifsc: add support of stm32mp23

Add support of stm32mp23 platform in RIFSC driver.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne

drivers: stm32_rifsc: add support of stm32mp23

Add support of stm32mp23 platform in RIFSC driver.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: add support of STM32MP21

Update RIMU table for SM32MP21.
RISAL is not supported on STM32MP21, so do not compile RISAL API in
RISFC for STM32MP21.

Signed-off-by: Thomas Bourgoi

drivers: stm32_rifsc: add support of STM32MP21

Update RIMU table for SM32MP21.
RISAL is not supported on STM32MP21, so do not compile RISAL API in
RISFC for STM32MP21.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: fix RIMU configuration parsing

The RIF configuration of the first RIMU was incorrectly parsed over and
over again for each RIMU. Fix this by using the index that represents
the

drivers: stm32_rifsc: fix RIMU configuration parsing

The RIF configuration of the first RIMU was incorrectly parsed over and
over again for each RIMU. Fix this by using the index that represents
the RIMU ID.

Fixes: cd187630b280 ("drivers: add stm32 RIFSC support")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: remove redundant and incorrect parsing of RIMU conf

In case we're not TDCID, we cannot configure RIMUs. Plus, the call was
redundant with the lines above.

Fixes: 471cec144fa3

drivers: stm32_rifsc: remove redundant and incorrect parsing of RIMU conf

In case we're not TDCID, we cannot configure RIMUs. Plus, the call was
redundant with the lines above.

Fixes: 471cec144fa3 ("drivers: stm32_rifsc: update RIFSC as a firewall controller")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: implement transient CID0 on AHB errata for RIMUs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_rifsc: implement transient CID0 on AHB errata for RIMUs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

When "st,errata-ahbrisab" is set in the device tree, RIMUs cannot hold
the CID0 value on the bus.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

Force authorize CID0 access on RISAB so that it can always access
memories protected by RISABs when the "st,errata-ahbrisab" property is
set in the device tree.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: remove semaphore acquisition when applying the conf

Remove the semaphore acquisition when applying the configuration
so that they are taken, if necessary, during the firewall b

drivers: stm32_rifsc: remove semaphore acquisition when applying the conf

Remove the semaphore acquisition when applying the configuration
so that they are taken, if necessary, during the firewall bus probe.
This avoids semaphores from being taken by OP-TEE when the peripheral
isn't used.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: add platform-specific abort handler

When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it
may be an abort generated by the SERC hardware block. Check if a
SERC Illegal

plat-stm32mp2: add platform-specific abort handler

When a data abort occurs and its fault type is FAULT_TYPE_IGNORE, it
may be an abort generated by the SERC hardware block. Check if a
SERC Illegal Access was caught and print the SERC register and panic()
if that is the case.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: add .set_memory_conf ops

Add the .set_memory_conf ops to be able to reconfigure memory regions
protected by RISABs dynamically.

Factorize the RIF configuration application.

S

drivers: stm32_risab: add .set_memory_conf ops

Add the .set_memory_conf ops to be able to reconfigure memory regions
protected by RISABs dynamically.

Factorize the RIF configuration application.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: rework regs_access_granted()

Rework regs_access_granted() to always authorize access to RISAB1/2
that can only be accessed by the Cortex-A35.

Also fix the sequence by isolatin

drivers: stm32_risab: rework regs_access_granted()

Rework regs_access_granted() to always authorize access to RISAB1/2
that can only be accessed by the Cortex-A35.

Also fix the sequence by isolating the case where the CID filtering is
not enabled.

Fixes: c413678c6ca6 ("drivers: stm32_risab: add RISAB internal memory firewall driver")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: stm32_etzpc: remove header file

Remove stm32_etzpc.h header file that is not required since the
declared and defined resources are used internally in stm32_etzpc.c

By the way, al

drivers: firewall: stm32_etzpc: remove header file

Remove stm32_etzpc.h header file that is not required since the
declared and defined resources are used internally in stm32_etzpc.c

By the way, also remove inclusion of stm32mp15-etzpc.h DT bindings
header file from stm32_rng.c where it is not needed.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_rifsc: add RISAL support for stm32mp25x platforms

Add RISAL driver support.

RISAL is a sub-feature of the RISFC which is responsible for the
isolation of hardware resources like memo

drivers: stm32_rifsc: add RISAL support for stm32mp25x platforms

Add RISAL driver support.

RISAL is a sub-feature of the RISFC which is responsible for the
isolation of hardware resources like memory or peripherals. RISALs are
simplified version of the RISAFs firewall controllers and cover the
LPSRAM1/2/3 embedded memories.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Gwenael Treuveur <gwenael.treuveur@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risaf: upgrade RISAF as a firewall controller

Register RISAF instances as firewall controllers with ops:
-acquire_memory_access() that checks if OP-TEE can access a region
specified i

drivers: stm32_risaf: upgrade RISAF as a firewall controller

Register RISAF instances as firewall controllers with ops:
-acquire_memory_access() that checks if OP-TEE can access a region
specified in a firewall query.
-set_conf() that allows the reconfiguration of a region.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: stm32_etzpc: add check_access handler

Implement .check_access handler in stm32_etzpc driver.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Patrick D

drivers: firewall: stm32_etzpc: add check_access handler

Implement .check_access handler in stm32_etzpc driver.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_rif: update and fix RIF configuration parsing

Fix the parsing of the RIF configuration by using device tree bindings,
when necessary. Generalize RIF bit fields and use them when deali

drivers: stm32_rif: update and fix RIF configuration parsing

Fix the parsing of the RIF configuration by using device tree bindings,
when necessary. Generalize RIF bit fields and use them when dealing
with generic RIF functions. Update drivers that use stm32_rif_parse_cfg()
accordingly.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Fixes: 1506f47af917 ("drivers: firewall: add stm32_rif driver for common RIF features")

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drivers: firewall: stm32_etzpc: add memory configuration firewall API

Implement the .set_memory_conf() firewall ops that allows to reconfigure
memory regions managed by the platform ETZPC firewall c

drivers: firewall: stm32_etzpc: add memory configuration firewall API

Implement the .set_memory_conf() firewall ops that allows to reconfigure
memory regions managed by the platform ETZPC firewall controller.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: firewall: add memory range firewall controller ops

Add a firewall driver operation handle and a firewall framework API
function to configure memory access rights, base on physical address
rang

core: firewall: add memory range firewall controller ops

Add a firewall driver operation handle and a firewall framework API
function to configure memory access rights, base on physical address
range arguments.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: firewall: stm32_etzpc: allow valid locked configuration

Change stm32_etzpc driver to not trigger an error when the
requested firewall configuration matches an already configured
and locked

drivers: firewall: stm32_etzpc: allow valid locked configuration

Change stm32_etzpc driver to not trigger an error when the
requested firewall configuration matches an already configured
and locked configuration.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: firewall: stm32_etzpc: pager SRAMs must be secure

STM32MP15 SRAMs used by pager can only be configured as secure access
only.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

drivers: firewall: stm32_etzpc: pager SRAMs must be secure

STM32MP15 SRAMs used by pager can only be configured as secure access
only.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: firewall: stm32_etzpc: fix DECPROT values

Correct sanitize_decprot_config() implementation: label values to
enumerated type etzpc_decprot_attributes are prefixed ETZPC_.

Fixes: 9c22da4b29d

drivers: firewall: stm32_etzpc: fix DECPROT values

Correct sanitize_decprot_config() implementation: label values to
enumerated type etzpc_decprot_attributes are prefixed ETZPC_.

Fixes: 9c22da4b29de ("firewall: stm32_etzpc: check consistency of RCC vs DECPROT secure config")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: firewall: stm32_etzpc: print DECPROT values as strings

Print ETZPC attribute strings instead of numerical value in trace
messages.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st

drivers: firewall: stm32_etzpc: print DECPROT values as strings

Print ETZPC attribute strings instead of numerical value in trace
messages.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: firewall: stm32_etzpc: explicit index in DECPROT string names

Explicit the indices assigned to DECPROT helper string names.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
R

drivers: firewall: stm32_etzpc: explicit index in DECPROT string names

Explicit the indices assigned to DECPROT helper string names.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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firewall: stm32_etzpc: check consistency of RCC vs DECPROT secure config

Ensures that when an ETZPC DECPROT configuration is secure (resp.
MCU isolated) that SoC RCC is also secure (resp. MCKPROT is

firewall: stm32_etzpc: check consistency of RCC vs DECPROT secure config

Ensures that when an ETZPC DECPROT configuration is secure (resp.
MCU isolated) that SoC RCC is also secure (resp. MCKPROT isolated).

This change helps to remove dependency on shared_resource.c driver
that is no longer needed since integration of the firewall framework.

By the way, fix include files order.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>

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drivers: use fdt_reg_info()

Use fdt_reg_info() instead of fdt_reg_base_address() and fdt_reg_size()
to optimize look up in the DT due to finding parent node.

Signed-off-by: Etienne Carriere <etienn

drivers: use fdt_reg_info()

Use fdt_reg_info() instead of fdt_reg_base_address() and fdt_reg_size()
to optimize look up in the DT due to finding parent node.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_etzpc: new driver to use firewall API

Implement stm32_etzpc.c driver in the firewall driver directory.
Use the new firewall API to populate the firewall bus and register
the ETZPC as

drivers: stm32_etzpc: new driver to use firewall API

Implement stm32_etzpc.c driver in the firewall driver directory.
Use the new firewall API to populate the firewall bus and register
the ETZPC as a firewall provider.

Implement a driver specific firewall bus probe that will
only probe secure peripherals and implement firewall exceptions for
which no firewall operations will be done when CFG_INSECURE is set.
This allows, for example, to share a console with the non-secure world
for development purposes.

The ETZPC driver register the following ops:
-set_conf
-acquire_access
-acquire_memory_access

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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