1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2024, STMicroelectronics 4 */ 5 6 #include <arm.h> 7 #include <config.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/stm32_gpio.h> 11 #include <drivers/stm32_rif.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/delay.h> 15 #include <kernel/dt.h> 16 #include <kernel/dt_driver.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm.h> 19 #include <libfdt.h> 20 #include <mm/core_memprot.h> 21 #include <stdbool.h> 22 #include <stdlib.h> 23 #include <stm32_util.h> 24 #include <trace.h> 25 26 #define _FMC_CFGR U(0x020) 27 #define _FMC_SECCFGR U(0x300) 28 #define _FMC_PRIVCFGR U(0x304) 29 #define _FMC_RCFGLOCKR U(0x308) 30 #define _FMC_CIDCFGR(x) (U(0x30C) + U(0x8) * (x)) 31 #define _FMC_SEMCR(x) (U(0x310) + U(0x8) * (x)) 32 /* 33 * CFGR register bitfields 34 */ 35 #define _FMC_CFGR_CLKDIV_MASK GENMASK_32(19, 16) 36 #define _FMC_CFGR_CLKDIV_SHIFT U(16) 37 #define _FMC_CFGR_CCLKEN BIT(20) 38 #define _FMC_CFGR_ENABLE BIT(31) 39 40 /* 41 * CIDCFGR register bitfields 42 */ 43 #define _FMC_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 44 #define _FMC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 45 #define _FMC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 46 _CIDCFGR_SEMEN | \ 47 _FMC_CIDCFGR_SCID_MASK |\ 48 _FMC_CIDCFGR_SEMWL_MASK) 49 50 /* 51 * PRIVCFGR register bitfields 52 */ 53 #define _FMC_PRIVCFGR_MASK GENMASK_32(5, 0) 54 55 /* 56 * RCFGLOCKR register bitfields 57 */ 58 #define _FMC_RCFGLOCKR_MASK GENMASK_32(5, 0) 59 60 /* 61 * SECCFGR register bitfields 62 */ 63 #define _FMC_SECCFGR_EN BIT(0) 64 #define _FMC_SECCFGR_MASK GENMASK_32(5, 0) 65 66 /* 67 * SEMCR register bitfields 68 */ 69 #define _FMC_SEMCR_SCID_MASK GENMASK_32(7, 5) 70 #define _FMC_SEMCR_SCID_SHIFT U(5) 71 72 /* 73 * Miscellaneous 74 */ 75 76 #define FMC_RIF_CONTROLLERS U(6) 77 78 #define FMC_NB_MAX_CID_SUPPORTED U(7) 79 80 #define FMC_NSEC_PER_SEC UL(1000000000) 81 82 struct fmc_pdata { 83 struct clk *fmc_clock; 84 struct pinctrl_state *pinctrl_d; 85 struct pinctrl_state *pinctrl_s; 86 struct rif_conf_data conf_data; 87 unsigned int nb_controller; 88 vaddr_t base; 89 uint32_t clk_period_ns; 90 bool cclken; 91 }; 92 93 static struct fmc_pdata *fmc_d; 94 95 static bool fmc_controller_is_secure(uint8_t controller) 96 { 97 return io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(controller); 98 } 99 100 static TEE_Result apply_rif_config(void) 101 { 102 TEE_Result res = TEE_ERROR_ACCESS_DENIED; 103 uint32_t cidcfgr = 0; 104 unsigned int i = 0; 105 106 res = clk_enable(fmc_d->fmc_clock); 107 if (res) 108 panic("Cannot access FMC clock"); 109 110 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) { 111 if (!(BIT(i) & fmc_d->conf_data.access_mask[0])) 112 continue; 113 114 /* 115 * Whatever the TDCID state, try to clear the configurable part 116 * of the CIDCFGR register. 117 * If TDCID, register will be cleared, if not, the clear will 118 * be ignored. 119 * When TDCID, OP-TEE should be the one to set the CID filtering 120 * configuration. Clearing previous configuration prevents 121 * undesired events during the only legitimate configuration. 122 */ 123 io_clrbits32(fmc_d->base + _FMC_CIDCFGR(i), 124 _FMC_CIDCFGR_CONF_MASK); 125 126 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); 127 128 /* Check if the controller is in semaphore mode */ 129 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 130 continue; 131 132 /* If not TDCID, we want to acquire semaphores assigned to us */ 133 res = stm32_rif_acquire_semaphore(fmc_d->base + _FMC_SEMCR(i), 134 FMC_NB_MAX_CID_SUPPORTED); 135 if (res) { 136 EMSG("Couldn't acquire semaphore for controller %u", i); 137 clk_disable(fmc_d->fmc_clock); 138 return res; 139 } 140 } 141 142 /* Security and privilege RIF configuration */ 143 io_clrsetbits32(fmc_d->base + _FMC_PRIVCFGR, _FMC_PRIVCFGR_MASK, 144 fmc_d->conf_data.priv_conf[0]); 145 io_clrsetbits32(fmc_d->base + _FMC_SECCFGR, _FMC_SECCFGR_MASK, 146 fmc_d->conf_data.sec_conf[0]); 147 148 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) { 149 if (!(BIT(i) & fmc_d->conf_data.access_mask[0])) 150 continue; 151 152 io_clrsetbits32(fmc_d->base + _FMC_CIDCFGR(i), 153 _FMC_CIDCFGR_CONF_MASK, 154 fmc_d->conf_data.cid_confs[i]); 155 156 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); 157 158 /* 159 * Take semaphore if the resource is in semaphore mode 160 * and secured 161 */ 162 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) || 163 !(io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(i))) { 164 res = 165 stm32_rif_release_semaphore(fmc_d->base + _FMC_SEMCR(i), 166 FMC_NB_MAX_CID_SUPPORTED); 167 if (res) { 168 EMSG("Couldn't release semaphore for res%u", i); 169 clk_disable(fmc_d->fmc_clock); 170 return res; 171 } 172 } else { 173 res = 174 stm32_rif_acquire_semaphore(fmc_d->base + _FMC_SEMCR(i), 175 FMC_NB_MAX_CID_SUPPORTED); 176 if (res) { 177 EMSG("Couldn't acquire semaphore for res%u", i); 178 clk_disable(fmc_d->fmc_clock); 179 return res; 180 } 181 } 182 } 183 184 /* 185 * Lock RIF configuration if configured. This cannot be undone until 186 * next reset. 187 */ 188 io_clrsetbits32(fmc_d->base + _FMC_RCFGLOCKR, _FMC_RCFGLOCKR_MASK, 189 fmc_d->conf_data.lock_conf[0]); 190 191 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 192 /* Check that RIF config are applied, panic otherwise */ 193 if ((io_read32(fmc_d->base + _FMC_PRIVCFGR) & 194 fmc_d->conf_data.access_mask[0]) != 195 fmc_d->conf_data.priv_conf[0]) { 196 EMSG("FMC controller priv conf is incorrect"); 197 panic(); 198 } 199 200 if ((io_read32(fmc_d->base + _FMC_SECCFGR) & 201 fmc_d->conf_data.access_mask[0]) != 202 fmc_d->conf_data.sec_conf[0]) { 203 EMSG("FMC controller sec conf is incorrect"); 204 panic(); 205 } 206 } 207 208 /* Disable the clock to allow RCC RIF re-configuration on this clock */ 209 clk_disable(fmc_d->fmc_clock); 210 211 return TEE_SUCCESS; 212 } 213 214 static TEE_Result parse_dt(const void *fdt, int node) 215 { 216 TEE_Result res = TEE_ERROR_GENERIC; 217 uint32_t rif_conf = 0; 218 unsigned int i = 0; 219 int lenp = 0; 220 const fdt32_t *cuint = NULL; 221 struct dt_node_info info = { }; 222 struct io_pa_va addr = { }; 223 int ctrl_node = 0; 224 225 fdt_fill_device_info(fdt, &info, node); 226 assert(info.reg != DT_INFO_INVALID_REG && 227 info.reg_size != DT_INFO_INVALID_REG_SIZE); 228 229 addr.pa = info.reg; 230 fmc_d->base = io_pa_or_va(&addr, info.reg_size); 231 232 res = clk_dt_get_by_index(fdt, node, 0, &fmc_d->fmc_clock); 233 if (res) 234 return res; 235 236 res = pinctrl_get_state_by_name(fdt, node, "default", 237 &fmc_d->pinctrl_d); 238 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 239 return res; 240 241 res = pinctrl_get_state_by_name(fdt, node, "sleep", 242 &fmc_d->pinctrl_s); 243 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 244 return res; 245 246 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 247 if (!cuint) 248 panic("No RIF configuration available"); 249 250 fmc_d->nb_controller = (unsigned int)(lenp / sizeof(uint32_t)); 251 assert(fmc_d->nb_controller <= FMC_RIF_CONTROLLERS); 252 253 fmc_d->conf_data.cid_confs = calloc(FMC_RIF_CONTROLLERS, 254 sizeof(uint32_t)); 255 fmc_d->conf_data.sec_conf = calloc(1, sizeof(uint32_t)); 256 fmc_d->conf_data.priv_conf = calloc(1, sizeof(uint32_t)); 257 fmc_d->conf_data.lock_conf = calloc(1, sizeof(uint32_t)); 258 fmc_d->conf_data.access_mask = calloc(1, sizeof(uint32_t)); 259 assert(fmc_d->conf_data.cid_confs && fmc_d->conf_data.sec_conf && 260 fmc_d->conf_data.priv_conf && fmc_d->conf_data.access_mask); 261 262 for (i = 0; i < fmc_d->nb_controller; i++) { 263 rif_conf = fdt32_to_cpu(cuint[i]); 264 265 stm32_rif_parse_cfg(rif_conf, &fmc_d->conf_data, 266 FMC_RIF_CONTROLLERS); 267 } 268 269 fdt_for_each_subnode(ctrl_node, fdt, node) { 270 int status = fdt_get_status(fdt, ctrl_node); 271 uint32_t bank = 0; 272 273 if (status == DT_STATUS_DISABLED) 274 continue; 275 276 if (fdt_read_uint32(fdt, ctrl_node, "reg", &bank) < 0) 277 return TEE_ERROR_BAD_PARAMETERS; 278 279 if (bank != 0) 280 continue; 281 282 if (fdt_getprop(fdt, ctrl_node, 283 "st,fmc2-ebi-cs-cclk-enable", NULL)) 284 fmc_d->cclken = true; 285 286 if (!fmc_d->cclken) 287 continue; 288 289 if (fdt_read_uint32(fdt, ctrl_node, 290 "st,fmc2-ebi-cs-clk-period-ns", 291 &fmc_d->clk_period_ns) < 0) 292 return TEE_ERROR_BAD_PARAMETERS; 293 } 294 295 return TEE_SUCCESS; 296 } 297 298 static TEE_Result __maybe_unused check_fmc_rif_conf(void) 299 { 300 unsigned int i = 0; 301 TEE_Result res = TEE_ERROR_GENERIC; 302 303 res = clk_enable(fmc_d->fmc_clock); 304 if (res) 305 panic("Cannot access FMC clock"); 306 307 if (fmc_controller_is_secure(0)) 308 goto end; 309 310 for (i = 1; i < fmc_d->nb_controller; i++) { 311 uint32_t cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); 312 uint32_t semcr = io_read32(fmc_d->base + _FMC_SEMCR(i)); 313 314 /* Check if a controller is secure */ 315 if (fmc_controller_is_secure(i)) { 316 res = TEE_ERROR_BAD_STATE; 317 goto end; 318 } 319 320 /* 321 * Check if a controller is shared with incorrect CID 322 * (!= RIF_CID1) 323 */ 324 res = stm32_rif_check_access(cidcfgr, semcr, 325 FMC_NB_MAX_CID_SUPPORTED, 326 RIF_CID1); 327 if (res) 328 break; 329 } 330 331 end: 332 clk_disable(fmc_d->fmc_clock); 333 334 return res; 335 } 336 337 static void configure_fmc(void) 338 { 339 uint32_t cidcfgr = 0; 340 uint32_t semcr = 0; 341 342 if (clk_enable(fmc_d->fmc_clock)) 343 panic("Cannot access FMC clock"); 344 345 semcr = io_read32(fmc_d->base + _FMC_SEMCR(0)); 346 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(0)); 347 348 /* 349 * If OP-TEE doesn't have access to the controller 0, 350 * then we don't want to try to enable the FMC. 351 */ 352 if (stm32_rif_check_access(cidcfgr, semcr, 353 FMC_NB_MAX_CID_SUPPORTED, RIF_CID1)) 354 goto end; 355 356 /* Check controller 0 access */ 357 if (!fmc_controller_is_secure(0)) { 358 DMSG("Controller 0 non-secure, FMC not enabled"); 359 goto end; 360 } 361 362 if (cidcfgr & _CIDCFGR_SEMEN && 363 stm32_rif_acquire_semaphore(fmc_d->base + _FMC_SEMCR(0), 364 FMC_NB_MAX_CID_SUPPORTED)) 365 panic("Couldn't acquire controller 0 semaphore"); 366 367 if (fmc_d->pinctrl_d && pinctrl_apply_state(fmc_d->pinctrl_d)) 368 panic("Could not apply FMC pinctrl"); 369 370 if (fmc_d->cclken) { 371 unsigned long hclk = clk_get_rate(fmc_d->fmc_clock); 372 unsigned long hclkp = FMC_NSEC_PER_SEC / (hclk / 1000); 373 unsigned long timing = DIV_ROUND_UP(fmc_d->clk_period_ns * 1000, 374 hclkp); 375 uint32_t clk_div = SHIFT_U32(1, _FMC_CFGR_CLKDIV_SHIFT); 376 377 if (timing > 1) { 378 timing--; 379 if (timing > 380 _FMC_CFGR_CLKDIV_MASK >> _FMC_CFGR_CLKDIV_SHIFT) 381 clk_div = _FMC_CFGR_CLKDIV_MASK; 382 else 383 clk_div = SHIFT_U32(timing, 384 _FMC_CFGR_CLKDIV_SHIFT); 385 } 386 387 io_clrsetbits32(fmc_d->base + _FMC_CFGR, 388 _FMC_CFGR_CLKDIV_MASK | _FMC_CFGR_CCLKEN, 389 clk_div | _FMC_CFGR_CCLKEN); 390 } 391 392 /* Set the FMC enable BIT */ 393 io_setbits32(fmc_d->base + _FMC_CFGR, _FMC_CFGR_ENABLE); 394 395 end: 396 clk_disable(fmc_d->fmc_clock); 397 } 398 399 static void fmc_setup(void) 400 { 401 if (apply_rif_config()) 402 panic("Failed to apply rif_config"); 403 404 /* Sanity check for FMC RIF config */ 405 assert(check_fmc_rif_conf()); 406 407 configure_fmc(); 408 } 409 410 static void fmc_suspend(void) 411 { 412 unsigned int i = 0; 413 414 if (clk_enable(fmc_d->fmc_clock)) 415 panic("Cannot access FMC clock"); 416 417 if (fmc_controller_is_secure(0) && fmc_d->pinctrl_s && 418 pinctrl_apply_state(fmc_d->pinctrl_s)) 419 panic(); 420 421 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) 422 fmc_d->conf_data.cid_confs[i] = 423 io_read32(fmc_d->base + _FMC_CIDCFGR(i)) & 424 _FMC_CIDCFGR_CONF_MASK; 425 426 fmc_d->conf_data.priv_conf[0] = 427 io_read32(fmc_d->base + _FMC_PRIVCFGR) & _FMC_PRIVCFGR_MASK; 428 fmc_d->conf_data.sec_conf[0] = 429 io_read32(fmc_d->base + _FMC_SECCFGR) & _FMC_SECCFGR_MASK; 430 fmc_d->conf_data.lock_conf[0] = 431 io_read32(fmc_d->base + _FMC_RCFGLOCKR) & _FMC_RCFGLOCKR_MASK; 432 fmc_d->conf_data.access_mask[0] = 433 GENMASK_32(FMC_RIF_CONTROLLERS - 1, 0); 434 435 clk_disable(fmc_d->fmc_clock); 436 } 437 438 static TEE_Result fmc_pm(enum pm_op op, unsigned int pm_hint, 439 const struct pm_callback_handle *pm_handle __unused) 440 { 441 if (pm_hint != PM_HINT_CONTEXT_STATE) 442 return TEE_SUCCESS; 443 444 if (op == PM_OP_RESUME) 445 fmc_setup(); 446 else 447 fmc_suspend(); 448 449 return TEE_SUCCESS; 450 } 451 452 static TEE_Result fmc_probe(const void *fdt, int node, 453 const void *compat_data __unused) 454 { 455 TEE_Result res = TEE_ERROR_GENERIC; 456 457 fmc_d = calloc(1, sizeof(*fmc_d)); 458 if (!fmc_d) 459 return TEE_ERROR_OUT_OF_MEMORY; 460 461 res = parse_dt(fdt, node); 462 if (res) 463 goto err; 464 465 fmc_setup(); 466 467 register_pm_core_service_cb(fmc_pm, NULL, "stm32-fmc"); 468 469 return TEE_SUCCESS; 470 err: 471 /* Free all allocated resources */ 472 free(fmc_d->conf_data.cid_confs); 473 free(fmc_d->conf_data.sec_conf); 474 free(fmc_d->conf_data.priv_conf); 475 free(fmc_d->conf_data.access_mask); 476 free(fmc_d); 477 478 return res; 479 } 480 481 static const struct dt_device_match stm32_fmc_match_table[] = { 482 { .compatible = "st,stm32mp25-fmc2-ebi" }, 483 { } 484 }; 485 486 DEFINE_DT_DRIVER(stm32_fmc_dt_driver) = { 487 .name = "stm32_fmc", 488 .match_table = stm32_fmc_match_table, 489 .probe = fmc_probe, 490 }; 491