drivers: ele: enable support for i.MX91

Enable ELE driver support for i.MX91.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: imx_mu: enable support for i.MX91

Enable MU driver support for i.MX91

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: add support for i.MX91 EVK

Add the support for i.MX91 EVK

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: add i.MX91 SoC ID

add i.MX91 SoC ID

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: use i.MX93 register file for i.MX91

Since i.MX91 is similar to i.MX93, use i.MX93 register file
for i.MX91.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Foriss

core: imx: use i.MX93 register file for i.MX91

Since i.MX91 is similar to i.MX93, use i.MX93 register file
for i.MX91.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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link.mk: generate version.o in link-out-dir

When source code is piped to compiler, then the
current working directory is left into debug
data. If the working directory is not the output
directory, t

link.mk: generate version.o in link-out-dir

When source code is piped to compiler, then the
current working directory is left into debug
data. If the working directory is not the output
directory, then mappings which strip absolute output
directory paths don't work.

Removes absolute build time paths from version.o
debug info.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Mikko Rapeli <mikko.rapeli@linaro.org>

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link.mk: use CFLAGS with version.o

Should be used by all compilations.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Mikko Rapeli <mikko.rapeli@linaro.org>

core: imx: add support for i.MX95 EVK

Add the support for i.MX95 EVK

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: add i.MX95 SoC ID

add i.MX95 SoC ID

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: imx: add i.MX95 registers

Add i.MX95 registers

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

core: kernel: Fix checking register convention r1/x1 value of transfer_list

According to recently firmware handsoff spec [1]'s
"Register usage at handoff boundary", Transfer List's signature value
w

core: kernel: Fix checking register convention r1/x1 value of transfer_list

According to recently firmware handsoff spec [1]'s
"Register usage at handoff boundary", Transfer List's signature value
was changed from 0x40_b10b (3 bytes) to 4a0f_b10b (4 bytes).

As updating of TL's signature, register value of x1/r1 should be:

In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b->masked value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).

Therefore, it requires to separate mask and shift value for register
convention version field when checking each r1/x1 value.

This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.

2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.

This patch is a breaking change. It works only TF-A is updated.

Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]
Fixes: 508e2476b232 ("core: update transfer list header and signature")
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: sama5d2: update NVMEM cells

According to the customer Fuse Matrix of sama5d2, the cell length
is 32 bytes.

Fixes: 6c6c4d9eb45d ("dts: sama5d2: add NVMEM die_id node")
Fixes: 8bd542fcb2ae ("dts

dts: sama5d2: update NVMEM cells

According to the customer Fuse Matrix of sama5d2, the cell length
is 32 bytes.

Fixes: 6c6c4d9eb45d ("dts: sama5d2: add NVMEM die_id node")
Fixes: 8bd542fcb2ae ("dts: sama5d2: add huk node for the NVMEM hardware unique key")
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Translate to PA when allocating PGT with MMU enabled

If MMU is enabled, core_mmu_pgt_alloc() returns virtual address of PGT
instead of physical address. Thus, it leads to some errors wh

core: riscv: Translate to PA when allocating PGT with MMU enabled

If MMU is enabled, core_mmu_pgt_alloc() returns virtual address of PGT
instead of physical address. Thus, it leads to some errors when we
invoke pa_to_ppn() with returned PGT which is actually the virtual
address of that PGT.

Fix it by checking whether MMU is enabled or not. If MMU is enabled, we
translate the returned PGT to its physical address.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: arm32: force CFG_LPAE_ADDR_SPACE_BITS=32

AArch32/Arm7 can only use 32 bits for virtual addresses so force that
configuration to avoid inconsistencies.

Signed-off-by: Jens Wiklander <jens.wikl

core: arm32: force CFG_LPAE_ADDR_SPACE_BITS=32

AArch32/Arm7 can only use 32 bits for virtual addresses so force that
configuration to avoid inconsistencies.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: mmu_v7: remove non-working ns-virtualization

Removes the nonworking CFG_NS_VIRTUALIZATION code from core_mmu_v7.c.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core: arm: mmu_v7: remove non-working ns-virtualization

Removes the nonworking CFG_NS_VIRTUALIZATION code from core_mmu_v7.c.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: mm: remove unused map_memarea_sections()

Remove the unused function map_memarea_sections().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etien

core: arm: mm: remove unused map_memarea_sections()

Remove the unused function map_memarea_sections().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: increase tmp stack for CFG_NS_VIRTUALIZATION

CFG_NS_VIRTUALIZATION requires slightly more stack when enabled so add
that to the group of conditions using the larger tmp stack.

Signed-off

core: arm: increase tmp stack for CFG_NS_VIRTUALIZATION

CFG_NS_VIRTUALIZATION requires slightly more stack when enabled so add
that to the group of conditions using the larger tmp stack.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: leverage qsort_int() in PMIC driver

Use recently added qsort_int() helper function.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.w

plat-stm32mp1: leverage qsort_int() in PMIC driver

Use recently added qsort_int() helper function.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: pager use SYSRAM last page if possible

Update stm32mp1 with pager TZSRAM size to use SYSRAM last page
now that pager implementation issue pager pageable boundary is
addressed.

Signed

plat-stm32mp1: pager use SYSRAM last page if possible

Update stm32mp1 with pager TZSRAM size to use SYSRAM last page
now that pager implementation issue pager pageable boundary is
addressed.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add SAES dependency on RNG clock for stm32mp13

Adds missing RNG clock resource in SAES and PKA nodes in stm32mp13
SoC DTSI files.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st

dts: stm32: add SAES dependency on RNG clock for stm32mp13

Adds missing RNG clock resource in SAES and PKA nodes in stm32mp13
SoC DTSI files.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: arm64: fix compiling warning when enable BTI.

Fix compiling warning in sm4_armv8a_ce_a64.S when CFG_CORE_BTI=y:
aarch64-none-linux-gnu-ld.bfd: out/core/arch/arm/crypto/sm4_armv8a_ce_a64.o:
war

core: arm64: fix compiling warning when enable BTI.

Fix compiling warning in sm4_armv8a_ce_a64.S when CFG_CORE_BTI=y:
aarch64-none-linux-gnu-ld.bfd: out/core/arch/arm/crypto/sm4_armv8a_ce_a64.o:
warning: BTI turned on by -z force-bti when all inputs do not have BTI in NOTE section.

Signed-off-by: wentao.sun <wentao.sun@amlogic.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm64: Fixing SHA3-224 failed when using ARMv8.2-A cryptographic extensions

The block size of SHA3-224 is 144 bytes. In sha3_armv8a_ce_a64.S, it is
reading 152 bytes and deriving incorrect re

core: arm64: Fixing SHA3-224 failed when using ARMv8.2-A cryptographic extensions

The block size of SHA3-224 is 144 bytes. In sha3_armv8a_ce_a64.S, it is
reading 152 bytes and deriving incorrect result.

Observing SHA3-224 failed on long input message.

o regression_4001.8 Hash case 7 algo 0x50000008
regression_4001.8 OK
o regression_4001.9 Hash case 8 algo 0x50000008
vendor/amlogic/common/optee_test/host/xtest/regression_4000.c:1336: out has an unexpected content:
Got
06:F9:E6:CB 65:6C:15:4B 04:79:00:72 E5:F0:61:24 ....el.K.y.r..a$
F6:DE:1E:F8 B6:DB:33:9F A5:0B:38:CF ......3...8.
Expected
AA:B2:3C:9E 7F:B9:D7:DA CE:FD:FD:0B 1A:E8:5A:B1 ..<...........Z.
37:4A:BF:F7 C4:E3:F7:55 6E:CA:E4:12 7J.....Un...
...
vendor/amlogic/common/optee_test/host/xtest/regression_4000.c:1388: out has an unexpected content:
Got
C8:8E:8D:D6 ....
Expected
AA:B2:3C:9E ..<.
vendor/amlogic/common/optee_test/host/xtest/regression_4000.c:1401: out has an unexpected content:

Signed-off-by: Matthew Shyu <matthew.shyu@amlogic.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: bottom half uart driver with non-secure virtualization

Enable the bottom half uart driver with FF-A and non-secure
virtualization enabled.

The console struct itr_handler and struct n

plat-vexpress: bottom half uart driver with non-secure virtualization

Enable the bottom half uart driver with FF-A and non-secure
virtualization enabled.

The console struct itr_handler and struct notif_driver are moved into
nexus memory as needed.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: make S-EL1 notifications virtualization-aware

Add new defines for the ABI functions FFA_NOTIFICATION_GET and
FFA_NOTIFICATION_INFO_GET to support a more complete implementation of
the ABI

core: ffa: make S-EL1 notifications virtualization-aware

Add new defines for the ABI functions FFA_NOTIFICATION_GET and
FFA_NOTIFICATION_INFO_GET to support a more complete implementation of
the ABI.

The bookkeeping of the notification state is moved into a guest specific
struct notif_vm_bitmap.

Asynchronous notification is enabled per guest. Each guest defines its
own notification ID to request bottom half processing.

The FFA_NOTIFICATION_INFO_GET handler is updated to be able to report
multiple guest IDs.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: make generic notifications virtualization-aware

Makes the generic notification handling aware of virtualization. Atomic
events are delivered with a guest_id parameter and asynchronous
notifica

core: make generic notifications virtualization-aware

Makes the generic notification handling aware of virtualization. Atomic
events are delivered with a guest_id parameter and asynchronous
notifications are started per guest_id.

struct notif_data is added as guest specific data to be able to track if
notifications are started for a guest.

While this patch compiles it doesn't work as intended without patches
handling the ABI specific side of things.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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