plat-k3: drivers: Change SA2UL_init service to service_init_crypto

Since commit 11d8578d93f0 ("core: arm: call call_driver_initcalls()
late"), driver_init is deferred and thread_update_canaries trie

plat-k3: drivers: Change SA2UL_init service to service_init_crypto

Since commit 11d8578d93f0 ("core: arm: call call_driver_initcalls()
late"), driver_init is deferred and thread_update_canaries tries to get
random_stack_canaries which requires the TRNG driver to be setup. Since
it was being setup as part of driver_init, it lead to crash on K3
platforms.

Change driver_init to service_init_crypto which is meant to be used for
initialization of crypto operations. Also, for the TISCI services to be
available before service_init_crypto, change init_ti_sci invocation to
early_init_late.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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core: riscv: Fix initial value of a0 in "detect_csr" ASM macro

To set initial value of the register a0 to 1, the assembly code should
be "li a0, 1" instead of "addi a0, a0, 1".

Signed-off-by: Alvin

core: riscv: Fix initial value of a0 in "detect_csr" ASM macro

To set initial value of the register a0 to 1, the assembly code should
be "li a0, 1" instead of "addi a0, a0, 1".

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_rif: add stm32_rif_access_violation_action()

This function should be used by peripherals capable on raising
access violation interrupts (SERC, IAC). The behavior of the platform
on su

drivers: stm32_rif: add stm32_rif_access_violation_action()

This function should be used by peripherals capable on raising
access violation interrupts (SERC, IAC). The behavior of the platform
on such event is platform-specific. Therefore, its definition must be
done at platform level.

Also add CFG_STM32_PANIC_ON_IAC_EVENT and CFG_STM32_PANIC_ON_SERC_EVENT
to choose if the platform should panic upon receiving an IAC or a
SERC event.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add SERC node in stm32mp251 SoC device tree file

Add the IAC node in the stm32mp251 SoC device tree file and default
enable it for all platforms.

Signed-off-by: Gatien Chevallier <gatie

dts: stm32: add SERC node in stm32mp251 SoC device tree file

Add the IAC node in the stm32mp251 SoC device tree file and default
enable it for all platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add IAC node in stm32mp251 SoC device tree file

Add the IAC node in the stm32mp251 SoC device tree file and default
enable it for all platforms.

Signed-off-by: Gatien Chevallier <gatien

dts: stm32: add IAC node in stm32mp251 SoC device tree file

Add the IAC node in the stm32mp251 SoC device tree file and default
enable it for all platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: default enable SERC peripheral

Default enable SERC peripheral on stm32mp2x platforms so that accesses
that would normally freeze the bus will be collected by the SERC
driver.

Signed-

plat-stm32mp2: default enable SERC peripheral

Default enable SERC peripheral on stm32mp2x platforms so that accesses
that would normally freeze the bus will be collected by the SERC
driver.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: default enable IAC on stm32mp2x platforms

Default enable IAC support on stm32mp2x platforms so that illegal
accesses are caught by OP-TEE.

Signed-off-by: Gatien Chevallier <gatien.ch

plat-stm32mp2: default enable IAC on stm32mp2x platforms

Default enable IAC support on stm32mp2x platforms so that illegal
accesses are caught by OP-TEE.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: call call_driver_initcalls() late

Calls call_early_initcalls() and call_service_initcalls() directly
instead of call_initcalls() from init_tee_runtime(). This allows
call_driver_initcalls

core: arm: call call_driver_initcalls() late

Calls call_early_initcalls() and call_service_initcalls() directly
instead of call_initcalls() from init_tee_runtime(). This allows
call_driver_initcalls() to be called with PAUTH enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add call_{early,service,driver}_initcalls()

Add more fine-grained replacements for call_initcalls() to enable
initcalls at several separate stages.

Signed-off-by: Jens Wiklander <jens.wikland

core: add call_{early,service,driver}_initcalls()

Add more fine-grained replacements for call_initcalls() to enable
initcalls at several separate stages.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: boot: use thread specific PAUTH keys

Use thread specific PAUTH keys during boot while using thread specific
stack pointer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked

core: arm: boot: use thread specific PAUTH keys

Use thread specific PAUTH keys during boot while using thread specific
stack pointer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: introduce boot_init_primary_final()

Introduce boot_init_primary_final() and move the call to
call_finalcalls() into that function.

This is needed in later patches to enabled PAUTH before

core: arm: introduce boot_init_primary_final()

Introduce boot_init_primary_final() and move the call to
call_finalcalls() into that function.

This is needed in later patches to enabled PAUTH before
boot_init_primary_final() is called.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: implement PL310 SMC protocol

When Linux runs in normal world, it expects the PL310 to be initially
disabled, and then invokes SMCs to enable it.
Let CFG_PL310_SIP_PROTOCOL=y, and the L2 ca

plat-sam: implement PL310 SMC protocol

When Linux runs in normal world, it expects the PL310 to be initially
disabled, and then invokes SMCs to enable it.
Let CFG_PL310_SIP_PROTOCOL=y, and the L2 cache will be left untouched
until the OS enables it.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: update core local flags in native_intr_handler

The AArch32 version of the native_intr_handler() macro has until now
called C function without updating the core local flags to indicate

core: arm32: update core local flags in native_intr_handler

The AArch32 version of the native_intr_handler() macro has until now
called C function without updating the core local flags to indicate that
the temporary stack is in use. This can lead to errors with
CFG_CORE_DEBUG_CHECK_STACKS=y so fix this by setting THREAD_CLF_TMP and
THREAD_CLF_FIQ or THREAD_CLF_IRQ as needed.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: fix use after free in PMIC driver

Fix PMIC regulator levels arrays handling that missed a pointer reset
after the buffer is freed. At runtime, pmic_list_voltages() handler
function us

plat-stm32mp1: fix use after free in PMIC driver

Fix PMIC regulator levels arrays handling that missed a pointer reset
after the buffer is freed. At runtime, pmic_list_voltages() handler
function uses that reference and is expected to allocate back the
buffer in case non-secure world requests voltage enumeration for the
related regulator.

Fixes: a7990eb02b82 ("plat-stm32mp1: set voltage list at pmic driver init")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: apply "-march" and "-mabi" options to assembler

Update platform-aflags-generic to include the -march option. Without
specifying -march, the assembler will enable the C extension by defa

core: riscv: apply "-march" and "-mabi" options to assembler

Update platform-aflags-generic to include the -march option. Without
specifying -march, the assembler will enable the C extension by default
and generate compressed instructions, even if CFG_RISCV_ISA_C=n.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: use configuration options for RISC-V extensions

RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, ena

core: riscv: use configuration options for RISC-V extensions

RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, enable RVC and FPU extension for QEMU virt machine.

Note that the RISC-V FPU for OP-TEE will be introduced later.
Enable FPU to temporarily bypass incompatible soft/hard-fp
linker errors.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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kernel/link.mk: fix missing build number in version string on first build

Fix an issue with the build number in the version string. While at it,
factor out the duplicated code into mk/macros.mk.

Be

kernel/link.mk: fix missing build number in version string on first build

Fix an issue with the build number in the version string. While at it,
factor out the duplicated code into mk/macros.mk.

Before:

$ rm -rf out/
$ make out/arm-plat-vexpress/core/version.o
UPD out/arm-plat-vexpress/core/.buildcount
GEN out/arm-plat-vexpress/core/version.o
cat: out/arm-plat-vexpress/core/.buildcount: No such file or directory

In addition to the error message, note the missing build number after the
hash sign:

$ strings out/arm-plat-vexpress/core/version.o | grep UTC
4.3.0-48-g9c97e7d52 (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) # Wed Aug 14 16:17:07 UTC 2024 arm

After:

$ rm -rf out/
$ make out/arm-plat-vexpress/core/version.o
UPD out/arm-plat-vexpress/core/.buildcount
GEN out/arm-plat-vexpress/core/version.o
$ strings out/arm-plat-vexpress/core/version.o | grep UTC
4.3.0-48-g9c97e7d52-dev (gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)) #1 Wed Aug 14 16:17:24 UTC 2024 arm

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: boot_clear_memtag(): use core_mmu_for_each_map()

Use core_mmu_for_each_map() in boot_clear_memtag() to iterate over each
memory region and clear memory tags for each matching region.

Pre

core: arm: boot_clear_memtag(): use core_mmu_for_each_map()

Use core_mmu_for_each_map() in boot_clear_memtag() to iterate over each
memory region and clear memory tags for each matching region.

Preparing for future changes where more than one memory region may use
the same memory type.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Zeroize unused parameters before thread_return_to_udomain()

Zeroize unused parameters before calling thread_return_to_udomain() to
avoid leaking information to the untrusted domain unin

core: riscv: Zeroize unused parameters before thread_return_to_udomain()

Zeroize unused parameters before calling thread_return_to_udomain() to
avoid leaking information to the untrusted domain unintentionally.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: increase size of abort stack to 4096

To avoid stack overruns with CFG_WITH_PAGER=y and
CFG_CORE_DEBUG_CHECK_STACKS=y increase the abort stack from 3072 to
4096.

Signed-off-by: Jens Wik

core: arm64: increase size of abort stack to 4096

To avoid stack overruns with CFG_WITH_PAGER=y and
CFG_CORE_DEBUG_CHECK_STACKS=y increase the abort stack from 3072 to
4096.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: mm: introduce struct memory_map

Introduce struct memory_map to keep track of the array of struct
tee_mmap_region, covering number of used entries and number of allocated
entries.

core_mmap_is

core: mm: introduce struct memory_map

Introduce struct memory_map to keep track of the array of struct
tee_mmap_region, covering number of used entries and number of allocated
entries.

core_mmap_is_end_of_table() and MEM_AREA_END are now unused so remove
them.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ffa: handle VM availability messages for SPs

The VM availability messages sent by the hypervisor to an SP should be
forwarded to the SP, if the SP has subscribed for these based on the SP
mani

core: ffa: handle VM availability messages for SPs

The VM availability messages sent by the hypervisor to an SP should be
forwarded to the SP, if the SP has subscribed for these based on the SP
manifest.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: ffa: read S-EL0 SP properties from manifest

So far the properties of S-EL0 SPs have been hardcoded when queried by
FFA_PARTITION_INFO_GET. This was supposed to be a temporary workaround,
so re

core: ffa: read S-EL0 SP properties from manifest

So far the properties of S-EL0 SPs have been hardcoded when queried by
FFA_PARTITION_INFO_GET. This was supposed to be a temporary workaround,
so replace this with reading the properties from the SP's manifest which
is the proper solution.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: arm: kern.ld.S: align .ARM.ex* sections

Make sure that the .ARM.exidx and .ARM.extab sections are 8 byte aligned
to work with CFG_CORE_SANITIZE_KADDRESS=y.

Signed-off-by: Jens Wiklander <jens

core: arm: kern.ld.S: align .ARM.ex* sections

Make sure that the .ARM.exidx and .ARM.extab sections are 8 byte aligned
to work with CFG_CORE_SANITIZE_KADDRESS=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: core_mmu_arch: fix PPN field extraction from PTE

The upper bits of page table entry may contain other fields
introduced since Priv. ISA spec. v1.11 (20211203), such as PBMT
and N bits,

core: riscv: core_mmu_arch: fix PPN field extraction from PTE

The upper bits of page table entry may contain other fields
introduced since Priv. ISA spec. v1.11 (20211203), such as PBMT
and N bits, thus PPN field should be masked out with PTE_PPN.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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