1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/st,stm32mp25-rcc.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 }; 25 }; 26 27 psci { 28 compatible = "arm,psci-1.0"; 29 method = "smc"; 30 }; 31 32 intc: interrupt-controller@4ac00000 { 33 compatible = "arm,cortex-a7-gic"; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0x0 0x4ac10000 0x0 0x1000>, 37 <0x0 0x4ac20000 0x0 0x2000>, 38 <0x0 0x4ac40000 0x0 0x2000>, 39 <0x0 0x4ac60000 0x0 0x2000>; 40 #address-cells = <1>; 41 }; 42 43 clocks { 44 clk_hse: clk-hse { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <24000000>; 48 }; 49 50 clk_hsi: clk-hsi { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <64000000>; 54 }; 55 56 clk_lse: clk-lse { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <32768>; 60 }; 61 62 clk_lsi: clk-lsi { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <32000>; 66 }; 67 68 clk_msi: clk-msi { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <4000000>; 72 }; 73 74 clk_i2sin: clk-i2sin { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <0>; 78 }; 79 80 clk_rcbsec: clk-rcbsec { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <64000000>; 84 }; 85 }; 86 87 soc@0 { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 interrupt-parent = <&intc>; 92 ranges = <0x0 0x0 0x0 0x80000000>; 93 94 hpdma1: dma-controller@40400000 { 95 compatible = "st,stm32-dma3"; 96 reg = <0x40400000 0x1000>; 97 #dma-cells = <4>; 98 status = "disabled"; 99 }; 100 101 hpdma2: dma-controller@40410000 { 102 compatible = "st,stm32-dma3"; 103 reg = <0x40410000 0x1000>; 104 #dma-cells = <4>; 105 status = "disabled"; 106 }; 107 108 hpdma3: dma-controller@40420000 { 109 compatible = "st,stm32-dma3"; 110 reg = <0x40420000 0x1000>; 111 #dma-cells = <4>; 112 status = "disabled"; 113 }; 114 115 ipcc1: mailbox@40490000 { 116 compatible = "st,stm32mp25-ipcc"; 117 reg = <0x40490000 0x400>; 118 status = "disabled"; 119 }; 120 121 rifsc: rifsc@42080000 { 122 compatible = "st,stm32mp25-rifsc"; 123 reg = <0x42080000 0x1000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 127 usart2: serial@400e0000 { 128 reg = <0x400e0000 0x400>; 129 status = "disabled"; 130 }; 131 }; 132 133 iac: iac@42090000 { 134 compatible = "st,stm32mp25-iac"; 135 reg = <0x42090000 0x400>; 136 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 137 }; 138 139 rcc: rcc@44200000 { 140 compatible = "st,stm32mp25-rcc", "syscon"; 141 reg = <0x44200000 0x10000>; 142 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 143 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 147 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 148 clock-names = "clk-hse", "clk-hsi", "clk-lse", 149 "clk-lsi", "clk-msi", "clk-i2sin"; 150 151 hsi_calibration: hsi-calibration { 152 compatible = "st,hsi-cal"; 153 st,cal_hsi_dev = <31>; 154 st,cal_hsi_ref = <1953>; 155 status = "disabled"; 156 }; 157 158 msi_calibration: msi-calibration { 159 compatible = "st,msi-cal"; 160 status = "disabled"; 161 }; 162 }; 163 164 pinctrl: pinctrl@44240000 { 165 #address-cells = <1>; 166 #size-cells = <1>; 167 compatible = "st,stm32mp257-pinctrl"; 168 ranges = <0 0x44240000 0xa0400>; 169 pins-are-numbered; 170 171 gpioa: gpio@44240000 { 172 gpio-controller; 173 #gpio-cells = <2>; 174 interrupt-controller; 175 #interrupt-cells = <2>; 176 reg = <0x0 0x400>; 177 clocks = <&rcc CK_BUS_GPIOA>; 178 st,bank-name = "GPIOA"; 179 status = "disabled"; 180 }; 181 182 gpiob: gpio@44250000 { 183 gpio-controller; 184 #gpio-cells = <2>; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 reg = <0x10000 0x400>; 188 clocks = <&rcc CK_BUS_GPIOB>; 189 st,bank-name = "GPIOB"; 190 status = "disabled"; 191 }; 192 193 gpioc: gpio@44260000 { 194 gpio-controller; 195 #gpio-cells = <2>; 196 interrupt-controller; 197 #interrupt-cells = <2>; 198 reg = <0x20000 0x400>; 199 clocks = <&rcc CK_BUS_GPIOC>; 200 st,bank-name = "GPIOC"; 201 status = "disabled"; 202 }; 203 204 gpiod: gpio@44270000 { 205 gpio-controller; 206 #gpio-cells = <2>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 reg = <0x30000 0x400>; 210 clocks = <&rcc CK_BUS_GPIOD>; 211 st,bank-name = "GPIOD"; 212 status = "disabled"; 213 }; 214 215 gpioe: gpio@44280000 { 216 gpio-controller; 217 #gpio-cells = <2>; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 reg = <0x40000 0x400>; 221 clocks = <&rcc CK_BUS_GPIOE>; 222 st,bank-name = "GPIOE"; 223 status = "disabled"; 224 }; 225 226 gpiof: gpio@44290000 { 227 gpio-controller; 228 #gpio-cells = <2>; 229 interrupt-controller; 230 #interrupt-cells = <2>; 231 reg = <0x50000 0x400>; 232 clocks = <&rcc CK_BUS_GPIOF>; 233 st,bank-name = "GPIOF"; 234 status = "disabled"; 235 }; 236 237 gpiog: gpio@442a0000 { 238 gpio-controller; 239 #gpio-cells = <2>; 240 interrupt-controller; 241 #interrupt-cells = <2>; 242 reg = <0x60000 0x400>; 243 clocks = <&rcc CK_BUS_GPIOG>; 244 st,bank-name = "GPIOG"; 245 status = "disabled"; 246 }; 247 248 gpioh: gpio@442b0000 { 249 gpio-controller; 250 #gpio-cells = <2>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 reg = <0x70000 0x400>; 254 clocks = <&rcc CK_BUS_GPIOH>; 255 st,bank-name = "GPIOH"; 256 status = "disabled"; 257 }; 258 259 gpioi: gpio@442c0000 { 260 gpio-controller; 261 #gpio-cells = <2>; 262 interrupt-controller; 263 #interrupt-cells = <2>; 264 reg = <0x80000 0x400>; 265 clocks = <&rcc CK_BUS_GPIOI>; 266 st,bank-name = "GPIOI"; 267 status = "disabled"; 268 }; 269 270 gpioj: gpio@442d0000 { 271 gpio-controller; 272 #gpio-cells = <2>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 reg = <0x90000 0x400>; 276 clocks = <&rcc CK_BUS_GPIOJ>; 277 st,bank-name = "GPIOJ"; 278 status = "disabled"; 279 }; 280 281 gpiok: gpio@442e0000 { 282 gpio-controller; 283 #gpio-cells = <2>; 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 reg = <0xa0000 0x400>; 287 clocks = <&rcc CK_BUS_GPIOK>; 288 st,bank-name = "GPIOK"; 289 status = "disabled"; 290 }; 291 }; 292 293 pinctrl_z: pinctrl-z@46200000 { 294 #address-cells = <1>; 295 #size-cells = <1>; 296 compatible = "st,stm32mp257-z-pinctrl"; 297 ranges = <0 0x46200000 0x400>; 298 pins-are-numbered; 299 300 gpioz: gpio@46200000 { 301 gpio-controller; 302 #gpio-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 reg = <0 0x400>; 306 clocks = <&rcc CK_BUS_GPIOZ>; 307 st,bank-name = "GPIOZ"; 308 st,bank-ioport = <11>; 309 status = "disabled"; 310 }; 311 }; 312 313 hsem: hwspinlock@46240000 { 314 compatible = "st,stm32mp25-hsem"; 315 reg = <0x46240000 0x400>; 316 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 317 status = "disabled"; 318 }; 319 320 ipcc2: mailbox@46250000 { 321 compatible = "st,stm32mp25-ipcc"; 322 reg = <0x46250000 0x400>; 323 status = "disabled"; 324 }; 325 326 fmc: memory-controller@48200000 { 327 #address-cells = <2>; 328 #size-cells = <1>; 329 compatible = "st,stm32mp25-fmc2-ebi"; 330 reg = <0x48200000 0x400>; 331 status = "disabled"; 332 333 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 334 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 335 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 336 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 337 <4 0 0x80000000 0x10000000>; /* NAND */ 338 }; 339 }; 340}; 341