plat-stm: fix flavor 'cannes'

Fixes: 8cd89706f19c ("plat-stm: beautify platform config")

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@l

plat-stm: fix flavor 'cannes'

Fixes: 8cd89706f19c ("plat-stm: beautify platform config")

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core_mmu.h: align comments with code

Comment mentions MEM_AREA_NS_SHM which does not exists. Instead
there are MEM_AREA_NSEC_SHM.
Also there was different order of memory areas in comment and
in enu

core_mmu.h: align comments with code

Comment mentions MEM_AREA_NS_SHM which does not exists. Instead
there are MEM_AREA_NSEC_SHM.
Also there was different order of memory areas in comment and
in enum definition.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: TA private memory does not include the memref parameters

This change limits ta_private_vmem_end to TA segments defined when
TA is loaded.

Currently 'ta_private_vmem_end' only used to prevent

core: TA private memory does not include the memref parameters

This change limits ta_private_vmem_end to TA segments defined when
TA is loaded.

Currently 'ta_private_vmem_end' only used to prevent a TA from exposing
its code/data/stack memory to another TA it invokes. A shared memory
buffer passed as TA invocation parameter is obviously not inside the TA
private memory an can be exposed to another TA.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu, GP tests)

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Remove legacy tee_common_unpg.h

Removes legacy file core/include/kernel/tee_common_unpg.h
and updates with new types etc as needed.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Teste

Remove legacy tee_common_unpg.h

Removes legacy file core/include/kernel/tee_common_unpg.h
and updates with new types etc as needed.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: FS: add new RPC functions

Add new RPC functions that returns proper error coded.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@lina

core: FS: add new RPC functions

Add new RPC functions that returns proper error coded.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm: enable generic gic support

Change generic boot to call gic_cpu_init() for secondary boot cores.

Attempt (bss cleared?) to assert gic driver was initialized before
gic_pu_init() is called.

plat-stm: enable generic gic support

Change generic boot to call gic_cpu_init() for secondary boot cores.

Attempt (bss cleared?) to assert gic driver was initialized before
gic_pu_init() is called.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm: discard orly2 flavor

stm default plavor is 96board_c2.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: J

plat-stm: discard orly2 flavor

stm default plavor is 96board_c2.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm: beautify platform config

Move platform config to platfom_config.h.
Remove local system_config.mk.

Add generic SCU SAC/NSAC registers bit fields definition.
Add generic PL310 control regis

plat-stm: beautify platform config

Move platform config to platfom_config.h.
Remove local system_config.mk.

Add generic SCU SAC/NSAC registers bit fields definition.
Add generic PL310 control register enable bit fields definition.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm: beautify source code

Move plat_cpu_reset_late() to C-source.
Move arm_cl2_config() to C-source.
Beautify main.c and rng_support.c.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro

plat-stm: beautify source code

Move plat_cpu_reset_late() to C-source.
Move arm_cl2_config() to C-source.
Beautify main.c and rng_support.c.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: mmu: avoid panic in check_pa_matches_va()

If check_pa_matches_va() is called before the user va range has been
defined with CFG_WITH_LPAE=y it will cause a panic during boot. This
change adds

core: mmu: avoid panic in check_pa_matches_va()

If check_pa_matches_va() is called before the user va range has been
defined with CFG_WITH_LPAE=y it will cause a panic during boot. This
change adds a function to test that user va range is defined before
reading it.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: avoid panic in thread_addr_is_in_stack()

Avoids panic in thread_addr_is_in_stack() by returning false
if there's no current thread.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: avoid panic in thread_addr_is_in_stack()

Avoids panic in thread_addr_is_in_stack() by returning false
if there's no current thread.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add RPC FS cache for payload data

Adds an RPC FS cache for payload data. Allocated RPC FS payload data isn't
free until the thread exits the current command. This allows reuse of the
memory al

core: add RPC FS cache for payload data

Adds an RPC FS cache for payload data. Allocated RPC FS payload data isn't
free until the thread exits the current command. This allows reuse of the
memory allocation, avoiding many needless entries of tee-supplicant.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: kern.ld.S: put the RO sections together

By putting all the ro sections together, we can easily mark them
as RO.

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Jens Wikla

core: arm: kern.ld.S: put the RO sections together

By putting all the ro sections together, we can easily mark them
as RO.

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: fix the ttb pa address setting

Using the real physic address to set the mmu ttbr, and don't rely on the
plat mapping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-

core_mmu: fix the ttb pa address setting

Using the real physic address to set the mmu ttbr, and don't rely on the
plat mapping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
[Rebased on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm/plat-imx: fix SCR initialization

Secure Configuration Register shall be initialized for all cores.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander

plat-stm/plat-imx: fix SCR initialization

Secure Configuration Register shall be initialized for all cores.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm32: unwind: print_stack(): fix unwind_state

print_stack() must save r7 and r11 in the unwind_state structure. Not
doing so will likely result in a crash dunring unwind.
Register r7 is typically u

arm32: unwind: print_stack(): fix unwind_state

print_stack() must save r7 and r11 in the unwind_state structure. Not
doing so will likely result in a crash dunring unwind.
Register r7 is typically used as a frame pointer by GCC in Thumb2 mode,
while r11 (a.k.a. fp) is the frame pointer in ARM mode.

Also, set PC to the beginning of print_stack() since there's no point
in going further inside the function.

Fixes: https://github.com/OP-TEE/optee_os/issues/1069
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm32: unwind: mark tee_svc_do_call() with .cantunwind

The assembly function tee_svc_do_call() manipulates the stack pointer
but does not use the proper unwind directives when doing so. As a
result,

arm32: unwind: mark tee_svc_do_call() with .cantunwind

The assembly function tee_svc_do_call() manipulates the stack pointer
but does not use the proper unwind directives when doing so. As a
result, the compiler can't generate proper unwind information. This can
lead to crashes or infinite loops if unwinding is performed at runtime.
Given that there is nothing of much interest below this function, we
simply add a .cantundwind directive to stop unwinding here.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm32: unwind: convert int to bool

The return status of unwind_tab() is used as a boolean, so change its
type.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Car

arm32: unwind: convert int to bool

The return status of unwind_tab() is used as a boolean, so change its
type.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm32: unwind: fix incorrect return status

After the unwind code was imported from FreeBSD sources, it was slightly
modified to invert some logic. One return slipped through.

Signed-off-by: Jerome

arm32: unwind: fix incorrect return status

After the unwind code was imported from FreeBSD sources, it was slightly
modified to invert some logic. One return slipped through.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix spinlock for ARMv7-A and AArch32

Failure to acquire exclusivity when storing locked value on a
spinlock should not yield to wait for an event, just attempting
'strex' execution again.

Tes

core: fix spinlock for ARMv7-A and AArch32

Failure to acquire exclusivity when storing locked value on a
spinlock should not yield to wait for an event, just attempting
'strex' execution again.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260/qemu)
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: pad tee-pager.bin to the actual end of data section

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: fix TA memory reference parameters mapping

This change fixes the TA buffer parameter mapping that gets clobbered
when a parameter of lower index relates to nonsecure memory while
a parameter o

core: fix TA memory reference parameters mapping

This change fixes the TA buffer parameter mapping that gets clobbered
when a parameter of lower index relates to nonsecure memory while
a parameter of higher index relates to a secure memory area.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mm: fix the user L1 mmu entries calculation

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.co

mm: fix the user L1 mmu entries calculation

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

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mtk: map entire MEM_AREA_NSEC_SHM area

Running MTK8173 panics in tee_entry_std just after mapping the
arguments. The reason for this is because only 1MB out of 2MB has been
mapped and therefore leav

mtk: map entire MEM_AREA_NSEC_SHM area

Running MTK8173 panics in tee_entry_std just after mapping the
arguments. The reason for this is because only 1MB out of 2MB has been
mapped and therefore leaving a gap between MEM_AREA_NSEC_SHM and
MEM_AREA_TA_RAM. I.e.,

DEBUG: [0x0] TEE-CORE:init_mem_map:398: type va 4
0xbc000000..0xbc0fffff pa 0xbdf00000..0xbdffffff size 0x100000

DEBUG: [0x0] TEE-CORE:init_mem_map:398: type va 3
0xbc200000..0xbdffffff pa 0xbe200000..0xbfffffff size 0x1e00000

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm: introduce b2260 (96boards/cannes)

Flavored 'b2260'.
Default no GDB boot, lock pl310, specific DDR size and UART instance.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2120/

plat-stm: introduce b2260 (96boards/cannes)

Flavored 'b2260'.
Default no GDB boot, lock pl310, specific DDR size and UART instance.

Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2120/b2260)
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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