1 /* 2 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <arm32.h> 29 #include <asc.h> 30 #include <console.h> 31 #include <drivers/pl011.h> 32 #include <io.h> 33 #include <kernel/generic_boot.h> 34 #include <kernel/misc.h> 35 #include <kernel/panic.h> 36 #include <kernel/pm_stubs.h> 37 #include <kernel/tz_ssvce_pl310.h> 38 #include <mm/core_mmu.h> 39 #include <mm/core_memprot.h> 40 #include <platform_config.h> 41 #include <stdint.h> 42 #include <tee/entry_std.h> 43 #include <tee/entry_fast.h> 44 #include <trace.h> 45 46 register_phys_mem(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CORE_MMU_DEVICE_SIZE); 47 register_phys_mem(MEM_AREA_IO_SEC, RNG_BASE, CORE_MMU_DEVICE_SIZE); 48 register_phys_mem(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, CORE_MMU_DEVICE_SIZE); 49 50 #if defined(PLATFORM_FLAVOR_b2260) 51 #define stm_tee_entry_std tee_entry_std 52 static bool ns_resources_ready(void) 53 { 54 return true; 55 } 56 #else 57 /* some nonsecure resource might not be ready (uart) */ 58 static int boot_is_completed __early_bss; 59 static bool ns_resources_ready(void) 60 { 61 return !!boot_is_completed; 62 } 63 static void stm_tee_entry_std(struct thread_smc_args *smc_args) 64 { 65 boot_is_completed = 1; 66 tee_entry_std(smc_args); 67 } 68 #endif 69 70 static void stm_fiq(void) 71 { 72 panic(); 73 } 74 75 static const struct thread_handlers handlers = { 76 .std_smc = stm_tee_entry_std, 77 .fast_smc = tee_entry_fast, 78 .fiq = stm_fiq, 79 .cpu_on = pm_panic, 80 .cpu_off = pm_panic, 81 .cpu_suspend = pm_panic, 82 .cpu_resume = pm_panic, 83 .system_off = pm_panic, 84 .system_reset = pm_panic, 85 }; 86 87 const struct thread_handlers *generic_boot_get_handlers(void) 88 { 89 return &handlers; 90 } 91 92 static vaddr_t console_base(void) 93 { 94 static void *va __early_bss; 95 96 if (cpu_mmu_enabled()) { 97 if (!va) 98 va = phys_to_virt(UART_CONSOLE_BASE, MEM_AREA_IO_NSEC); 99 return (vaddr_t)va; 100 } 101 return UART_CONSOLE_BASE; 102 } 103 104 void console_init(void) 105 { 106 } 107 108 void console_putc(int ch) 109 { 110 if (ns_resources_ready()) { 111 if (ch == '\n') 112 __asc_xmit_char('\r', console_base()); 113 __asc_xmit_char((char)ch, console_base()); 114 } 115 } 116 117 void console_flush(void) 118 { 119 if (ns_resources_ready()) 120 __asc_flush(console_base()); 121 } 122 123 vaddr_t pl310_base(void) 124 { 125 static void *va __early_bss; 126 127 if (cpu_mmu_enabled()) { 128 if (!va) 129 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 130 return (vaddr_t)va; 131 } 132 return PL310_BASE; 133 } 134 135 void arm_cl2_config(vaddr_t pl310) 136 { 137 uint32_t v; 138 /* pl310 off */ 139 write32(0, pl310 + PL310_CTRL); 140 141 /* 142 * TAG RAM Control Register 143 * 144 * bit[10:8]:1 - 2 cycle of write accesses latency 145 * bit[6:4]:1 - 2 cycle of read accesses latency 146 * bit[2:0]:1 - 2 cycle of setup latency 147 */ 148 v = read32(pl310 + PL310_TAG_RAM_CTRL); 149 v &= 0xFFFFF888; 150 v |= 0xFFFFF999; 151 write32(v, pl310 + PL310_TAG_RAM_CTRL); 152 153 /* 154 * DATA RAM Control Register 155 * 156 * bit[10:8]:2 - 3 cycle of write accesses latency 157 * bit[6:4]:2 - 3 cycle of read accesses latency 158 * bit[2:0]:2 - 3 cycle of setup latency 159 */ 160 v = read32(pl310 + PL310_DATA_RAM_CTRL); 161 v &= 0xFFFFF888; 162 v |= 0xFFFFFAAA; 163 write32(v, pl310 + PL310_DATA_RAM_CTRL); 164 165 /* 166 * Auxiliary Control Register 167 * 168 * I/Dcache prefetch enabled (bit29:28=2b11) 169 * NS can access interrupts (bit27=1) 170 * NS can lockown cache lines (bit26=1) 171 * Pseudo-random replacement policy (bit25=0) 172 * Force write allocated (default) 173 * Shared attribute internally ignored (bit22=1, bit13=0) 174 * Parity disabled (bit21=0) 175 * Event monitor disabled (bit20=0) 176 * Set or preserved way config: size (bit19:17), ass (bit16) 177 * Store buffer device limitation enabled (bit11=1) 178 * Cacheable accesses have high prio (bit10=0) 179 * Full Line Zero (FLZ) disabled (bit0=0) 180 */ 181 v = PL310_AUX_CTRL_INIT; 182 write32(v, pl310 + PL310_AUX_CTRL); 183 184 /* 185 * Prefetch Control Register 186 * 187 * Double linefill disabled (bit30=0) 188 * I/D prefetch enabled (bit29:28=2b11) 189 * Prefetch drop enabled (bit24=1) 190 * Incr double linefill disable (bit23=0) 191 * Prefetch offset = 7 (bit4:0) 192 */ 193 write32(0x31000007, pl310 + PL310_PREFETCH_CTRL); 194 195 /* 196 * Power Register 197 * 198 * Dynamic clock gating enabled 199 * Standby mode enabled 200 */ 201 write32(0x00000003, pl310 + PL310_POWER_CTRL); 202 203 /* invalidate all pl310 cache ways */ 204 arm_cl2_invbyway(pl310); 205 } 206 207 void plat_cpu_reset_late(void) 208 { 209 int i; 210 211 assert(!cpu_mmu_enabled()); 212 213 /* Allow NSec to manage FIQ/Imprecise abort (SCR[FW]=1, SCR[AW]=1) */ 214 write_scr(SCR_AW | SCR_FW); 215 216 if (get_core_pos()) 217 return; 218 219 /* both secure CPU access SCU */ 220 write32(3, SCU_BASE + SCU_SAC); 221 222 /* both nonsec cpu access SCU, private and global timer */ 223 write32(0x333, SCU_BASE + SCU_NSAC); 224 225 /* SCU Filtering End Address register */ 226 write32(CPU_PORT_FILT_END, SCU_BASE + SCU_FILT_EA); 227 write32(CPU_PORT_FILT_START, SCU_BASE + SCU_FILT_SA); 228 229 /* 230 * SCU Control Register : CTRL = 0x00000065 231 * - ic stanby enable=1 232 * - scu standby enable=1 233 * - scu enable=1 234 */ 235 write32(0x0065, SCU_BASE + SCU_CTRL); 236 237 /* 238 * - All external interrupts are NonSecure. 239 */ 240 for (i = 0; i < (31 * 4); i += 4) 241 write32(0xFFFFFFFF, GIC_DIST_BASE + GIC_DIST_ISR1 + i); 242 243 /* PL310 Memory Controller port filtering */ 244 write32(CPU_PORT_FILT_END, pl310_base() + PL310_ADDR_FILT_END); 245 write32(CPU_PORT_FILT_START | 1, pl310_base() + PL310_ADDR_FILT_START); 246 } 247