1 /* 2 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <arm32.h> 29 #include <asc.h> 30 #include <console.h> 31 #include <drivers/pl011.h> 32 #include <io.h> 33 #include <kernel/generic_boot.h> 34 #include <kernel/misc.h> 35 #include <kernel/panic.h> 36 #include <kernel/pm_stubs.h> 37 #include <kernel/tz_ssvce_pl310.h> 38 #include <mm/core_mmu.h> 39 #include <mm/core_memprot.h> 40 #include <platform_config.h> 41 #include <stdint.h> 42 #include <tee/entry_std.h> 43 #include <tee/entry_fast.h> 44 #include <trace.h> 45 #include <util.h> 46 47 register_phys_mem(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CORE_MMU_DEVICE_SIZE); 48 register_phys_mem(MEM_AREA_IO_SEC, RNG_BASE, CORE_MMU_DEVICE_SIZE); 49 register_phys_mem(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, CORE_MMU_DEVICE_SIZE); 50 51 #if defined(PLATFORM_FLAVOR_b2260) 52 #define stm_tee_entry_std tee_entry_std 53 static bool ns_resources_ready(void) 54 { 55 return true; 56 } 57 #else 58 /* some nonsecure resource might not be ready (uart) */ 59 static int boot_is_completed __early_bss; 60 static bool ns_resources_ready(void) 61 { 62 return !!boot_is_completed; 63 } 64 static void stm_tee_entry_std(struct thread_smc_args *smc_args) 65 { 66 boot_is_completed = 1; 67 tee_entry_std(smc_args); 68 } 69 #endif 70 71 static void stm_fiq(void) 72 { 73 panic(); 74 } 75 76 static const struct thread_handlers handlers = { 77 .std_smc = stm_tee_entry_std, 78 .fast_smc = tee_entry_fast, 79 .fiq = stm_fiq, 80 .cpu_on = pm_panic, 81 .cpu_off = pm_panic, 82 .cpu_suspend = pm_panic, 83 .cpu_resume = pm_panic, 84 .system_off = pm_panic, 85 .system_reset = pm_panic, 86 }; 87 88 const struct thread_handlers *generic_boot_get_handlers(void) 89 { 90 return &handlers; 91 } 92 93 static vaddr_t console_base(void) 94 { 95 static void *va __early_bss; 96 97 if (cpu_mmu_enabled()) { 98 if (!va) 99 va = phys_to_virt(UART_CONSOLE_BASE, MEM_AREA_IO_NSEC); 100 return (vaddr_t)va; 101 } 102 return UART_CONSOLE_BASE; 103 } 104 105 void console_init(void) 106 { 107 } 108 109 void console_putc(int ch) 110 { 111 if (ns_resources_ready()) { 112 if (ch == '\n') 113 __asc_xmit_char('\r', console_base()); 114 __asc_xmit_char((char)ch, console_base()); 115 } 116 } 117 118 void console_flush(void) 119 { 120 if (ns_resources_ready()) 121 __asc_flush(console_base()); 122 } 123 124 vaddr_t pl310_base(void) 125 { 126 static void *va __early_bss; 127 128 if (cpu_mmu_enabled()) { 129 if (!va) 130 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 131 return (vaddr_t)va; 132 } 133 return PL310_BASE; 134 } 135 136 void arm_cl2_config(vaddr_t pl310) 137 { 138 /* pl310 off */ 139 write32(0, pl310 + PL310_CTRL); 140 141 /* config PL310 */ 142 write32(PL310_TAG_RAM_CTRL_INIT, pl310 + PL310_TAG_RAM_CTRL); 143 write32(PL310_DATA_RAM_CTRL_INIT, pl310 + PL310_DATA_RAM_CTRL); 144 write32(PL310_AUX_CTRL_INIT, pl310 + PL310_AUX_CTRL); 145 write32(PL310_PREFETCH_CTRL_INIT, pl310 + PL310_PREFETCH_CTRL); 146 write32(PL310_POWER_CTRL_INIT, pl310 + PL310_POWER_CTRL); 147 148 /* invalidate all pl310 cache ways */ 149 arm_cl2_invbyway(pl310); 150 } 151 152 void plat_cpu_reset_late(void) 153 { 154 int i; 155 156 assert(!cpu_mmu_enabled()); 157 158 /* Allow NSec to manage FIQ/Imprecise abort (SCR[FW]=1, SCR[AW]=1) */ 159 write_scr(SCR_AW | SCR_FW); 160 161 if (get_core_pos()) 162 return; 163 164 write32(SCU_SAC_INIT, SCU_BASE + SCU_SAC); 165 write32(SCU_NSAC_INIT, SCU_BASE + SCU_NSAC); 166 write32(CPU_PORT_FILT_END, SCU_BASE + SCU_FILT_EA); 167 write32(CPU_PORT_FILT_START, SCU_BASE + SCU_FILT_SA); 168 write32(SCU_CTRL_INIT, SCU_BASE + SCU_CTRL); 169 170 write32(CPU_PORT_FILT_END, pl310_base() + PL310_ADDR_FILT_END); 171 write32(CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT, 172 pl310_base() + PL310_ADDR_FILT_START); 173 174 /* default: all SPIs are nonsecure */ 175 for (i = 0; i < (31 * 4); i += 4) 176 write32(0xFFFFFFFF, GIC_DIST_BASE + GIC_DIST_ISR1 + i); 177 } 178