1/* 2 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <arm32.h> 29#include <arm32_macros.S> 30#include <asm.S> 31#include <kernel/tz_ssvce_def.h> 32#include <kernel/unwind.h> 33#include <platform_config.h> 34 35.section .text 36.balign 4 37.code 32 38 39/* 40 * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function 41 * 42 * If PL310 supports FZLW, enable also FZL in A9 core 43 * 44 * Use scratables registers R0-R3. 45 * No stack usage. 46 * LR store return address. 47 * Trap CPU in case of error. 48 * TODO: to be moved to PL310 code (tz_svce_pl310.S ?) 49 */ 50FUNC arm_cl2_enable , : 51UNWIND( .fnstart) 52 53 /* Enable PL310 ctrl -> only set lsb bit */ 54 mov r1, #0x1 55 str r1, [r0, #PL310_CTRL] 56 57 /* if L2 FLZW enable, enable in L1 */ 58 ldr r1, [r0, #PL310_AUX_CTRL] 59 tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */ 60 read_actlr r0 61 orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */ 62 write_actlr r0 63 64 mov pc, lr 65 66UNWIND( .fnend) 67END_FUNC arm_cl2_enable 68 69/* 70 * Cortex A9 configuration early configuration 71 * 72 * Use scratables registers R0-R3. 73 * No stack usage. 74 * LR store return address. 75 * Trap CPU in case of error. 76 */ 77FUNC plat_cpu_reset_early , : 78UNWIND( .fnstart) 79 80 /* 81 * Mandated HW config loaded 82 * 83 * SCTLR = 0x00004000 84 * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin) 85 * 86 * ACTRL = 0x00000041 87 * - core always in full SMP (FW bit0=1, SMP bit6=1) 88 * - L2 write full line of zero disabled (bit3=0) 89 * (keep WFLZ low. Will be set once outer L2 is ready) 90 * 91 * NSACR = 0x00020C00 92 * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) 93 * - Nsec can lockdown TLB (TL bit17=1) 94 * - NSec cannot access PLE (PLE bit16=0) 95 * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) 96 * 97 * PCR = 0x00000001 98 * - no change latency, enable clk gating 99 */ 100 movw r0, #0x4000 101 movt r0, #0x0000 102 write_sctlr r0 103 104 movw r0, #0x0041 105 movt r0, #0x0000 106 write_actlr r0 107 108 movw r0, #0x0C00 109 movt r0, #0x0002 110 write_nsacr r0 111 112 movw r0, #0x0000 113 movt r0, #0x0001 114 write_pcr r0 115 116 /* 117 * GIC configuration 118 * 119 * Register ICDISR0 = 0xFFFFFFFF 120 * - All local interrupts are NonSecure. 121 * 122 * Register ICCPMR = 0xFFFFFFFF 123 */ 124 125 ldr r0, =GIC_DIST_BASE 126 mov r1, #0xFFFFFFFF 127 str r1, [r0, #GIC_DIST_ISR0] 128 129 ldr r0, =GIC_CPU_BASE 130 mov r1, #0xFFFFFFFF 131 str r1, [r0, #CORE_ICC_ICCPMR] 132 133 mov pc, lr 134 135UNWIND( .fnend) 136END_FUNC plat_cpu_reset_early 137 138