core: panic at unexpected smc return

Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at

core: panic at unexpected smc return

Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot

To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: generate gicv3 register access code

Replaces the hand crafted system register code in <arm32.h> with
generated code based on arm32_gicv3_sysreg.txt which is extracted from
The ARM Gener

core: arm32: generate gicv3 register access code

Replaces the hand crafted system register code in <arm32.h> with
generated code based on arm32_gicv3_sysreg.txt which is extracted from
The ARM Generic Interrupt Controller Architecture Specification GIC
architecture version 3.0 and version 4.0.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: generate system register access code

Replaces the hand crafted system register code in <arm32.h> and
<arm32_macros.S> with generated code based on arm32_sysreg.txt which is
extracted fr

core: arm32: generate system register access code

Replaces the hand crafted system register code in <arm32.h> and
<arm32_macros.S> with generated code based on arm32_sysreg.txt which is
extracted from the ARM Architecture Reference Manual.

The remaining hand crafted code for cp15 accesses is not covered by the
ARM Architecture Reference Manual.

A script is added to generate both assembly macros and static inline
functions to access the system registers.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename read_idpfr1() to read_id_pfr1()

Renames the assembly macro read_idpfr1() to read_id_pfr1() to use the
real register name.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Si

core: rename read_idpfr1() to read_id_pfr1()

Renames the assembly macro read_idpfr1() to read_id_pfr1() to use the
real register name.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: sm: initialize PMCR.DP to 1 and save/restore PMCR

Introduce CFG_SM_NO_CYCLE_COUNTING to intitialize PMCR.DP to 1 and
save/restore PMCR on world switch. Similar to what is done in ARM TF
c

core: arm: sm: initialize PMCR.DP to 1 and save/restore PMCR

Introduce CFG_SM_NO_CYCLE_COUNTING to intitialize PMCR.DP to 1 and
save/restore PMCR on world switch. Similar to what is done in ARM TF
commit 3e61b2b54336 ("Init and save / restore of PMCR_EL0 / PMCR") [1].

The purpose of this is to (hopefully) make attacks such as CLKSCREW [2]
harder to mount, although it is likely that timing information could be
obtained via other means.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Link: [1] https://github.com/ARM-software/arm-trusted-firmware/commit/3e61b2b54336
Link: [2] https://www.usenix.org/system/files/conference/usenixsecurity17/sec17-tang.pdf
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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Remove license notice from STMicroelectronics files

Since a while the source files license info are defined by SPDX
identifiers. We can safely remove the verbose license text from the
files that are

Remove license notice from STMicroelectronics files

Since a while the source files license info are defined by SPDX
identifiers. We can safely remove the verbose license text from the
files that are owned by either only STMicroelectronics or only both
Linaro and STMicroelectronics.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm32: sm: init CNTVOFF

There is an property "arm,cpu-registers-not-fw-configured" in Linux side,
that could workaround the issue that firmare initialize CNTVOFF.

But if use that property, virtuali

arm32: sm: init CNTVOFF

There is an property "arm,cpu-registers-not-fw-configured" in Linux side,
that could workaround the issue that firmare initialize CNTVOFF.

But if use that property, virtualization support will be break in linux.

Also without CNTVOFF or that property no defined, kernel could not
boot up on i.MX7D with two cores.

So we init CNTVOFF in OP-TEE to make kernel work well.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: arm32_macros.S: add {read,write}_ttbr0_64bit

Adds the macros read_ttbr0_64bit and write_ttbr0_64bit

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <

core: arm32_macros.S: add {read,write}_ttbr0_64bit

Adds the macros read_ttbr0_64bit and write_ttbr0_64bit

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32_macros.S: add {read,write}_tpidrprw

Adds the assembly macros write_tpidrprw and read_tpidrprw to access the
TPIDRPRW register.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org

core: arm32_macros.S: add {read,write}_tpidrprw

Adds the assembly macros write_tpidrprw and read_tpidrprw to access the
TPIDRPRW register.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: psci: add suspend resume common functions

Add cpu suspend/resume common functions.

Platform psci suspend functions need to call
sm_pm_cpu_suspend(arg, platform_suspend) to runs into susp

core: arm: psci: add suspend resume common functions

Add cpu suspend/resume common functions.

Platform psci suspend functions need to call
sm_pm_cpu_suspend(arg, platform_suspend) to runs into suspend.

The i.MX flow is:
psci_cpu_suspend->imx7_cpu_suspend->sm_pm_cpu_suspend(arg, func)
The "func" runs in on-chip ram that not losing power when
system runs into suspend or low power state. Argument "arg" is
passed to function "func" as argument through register "r0".

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm32: fix assembly macro mov_imm

The assembly macro mov_imm incorrectly uses the "mov" instruction to
load 16 bits of immediate data. This patch fixes the macro to use the
"movw" instruction

core: arm32: fix assembly macro mov_imm

The assembly macro mov_imm incorrectly uses the "mov" instruction to
load 16 bits of immediate data. This patch fixes the macro to use the
"movw" instruction instead.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add tlbi and dsb instructions

Add 32bit and 64bit dsbish and dsbishst instructions.
Add 32bit write_tlbimvaais macro for TLB maintenance.

Signed-off-by: Etienne Carriere <etienne.carriere@lin

core: add tlbi and dsb instructions

Add 32bit and 64bit dsbish and dsbishst instructions.
Add 32bit write_tlbimvaais macro for TLB maintenance.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32_macros.S: add cache related macros

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm32_macros.S: sort macros

Sorts macros and fixes the macro write_bpial

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm32_macros: sort based on the CRn

Sort based on CRn

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm: add more cp15 register access macros

Add more cp15 register access macros.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm32: add mov_imm assembly macro

Adds mov_imm assembly macro to load 32-bit immediate values into a
register.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens

core: arm32: add mov_imm assembly macro

Adds mov_imm assembly macro to load 32-bit immediate values into a
register.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: invalidate i-cache inner shareable

When invalidating i-cache and branch predictor use inner shareable
(icialluis and bpiallis) versions of the operations to make it visible
to other cores

core: arm: invalidate i-cache inner shareable

When invalidating i-cache and branch predictor use inner shareable
(icialluis and bpiallis) versions of the operations to make it visible
to other cores.

Fixes occasional problem with pager with multiple active threads.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (HiKey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Rename arm32 architecture to arm

Renames arm32 directories to arm.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Reviewed-by

Rename arm32 architecture to arm

Renames arm32 directories to arm.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (QEMU platform)

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