1/* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Please keep them sorted based on the CRn register */ 29 30 .macro read_ctr reg 31 mrc p15, 0, \reg, c0, c0, 1 32 .endm 33 34 .macro read_mpidr reg 35 mrc p15, 0, \reg, c0, c0, 5 36 .endm 37 38 .macro read_sctlr reg 39 mrc p15, 0, \reg, c1, c0, 0 40 .endm 41 42 .macro write_sctlr reg 43 mcr p15, 0, \reg, c1, c0, 0 44 .endm 45 46 .macro write_actlr reg 47 mcr p15, 0, \reg, c1, c0, 1 48 .endm 49 50 .macro read_actlr reg 51 mrc p15, 0, \reg, c1, c0, 1 52 .endm 53 54 .macro write_cpacr reg 55 mcr p15, 0, \reg, c1, c0, 2 56 .endm 57 58 .macro read_cpacr reg 59 mrc p15, 0, \reg, c1, c0, 2 60 .endm 61 62 .macro read_scr reg 63 mrc p15, 0, \reg, c1, c1, 0 64 .endm 65 66 .macro write_scr reg 67 mcr p15, 0, \reg, c1, c1, 0 68 .endm 69 70 .macro write_nsacr reg 71 mcr p15, 0, \reg, c1, c1, 2 72 .endm 73 74 .macro read_nsacr reg 75 mrc p15, 0, \reg, c1, c1, 2 76 .endm 77 78 .macro write_ttbr0 reg 79 mcr p15, 0, \reg, c2, c0, 0 80 .endm 81 82 .macro read_ttbr0 reg 83 mrc p15, 0, \reg, c2, c0, 0 84 .endm 85 86 .macro write_ttbr1 reg 87 mcr p15, 0, \reg, c2, c0, 1 88 .endm 89 90 .macro read_ttbr1 reg 91 mrc p15, 0, \reg, c2, c0, 1 92 .endm 93 94 .macro write_ttbcr reg 95 mcr p15, 0, \reg, c2, c0, 2 96 .endm 97 98 .macro read_ttbcr reg 99 mrc p15, 0, \reg, c2, c0, 2 100 .endm 101 102 103 .macro write_dacr reg 104 mcr p15, 0, \reg, c3, c0, 0 105 .endm 106 107 .macro read_dacr reg 108 mrc p15, 0, \reg, c3, c0, 0 109 .endm 110 111 .macro read_dfsr reg 112 mrc p15, 0, \reg, c5, c0, 0 113 .endm 114 115 .macro write_icialluis 116 /* 117 * Invalidate all instruction caches to PoU, Inner Shareable 118 * (register ignored) 119 */ 120 mcr p15, 0, r0, c7, c1, 0 121 .endm 122 123 .macro write_bpiallis 124 /* 125 * Invalidate entire branch predictor array, Inner Shareable 126 * (register ignored) 127 */ 128 mcr p15, 0, r0, c7, c1, 6 129 .endm 130 131 .macro write_iciallu 132 /* Invalidate all instruction caches to PoU (register ignored) */ 133 mcr p15, 0, r0, c7, c5, 0 134 .endm 135 136 .macro write_icimvau reg 137 /* Instruction cache invalidate by MVA */ 138 mcr p15, 0, \reg, c7, c5, 1 139 .endm 140 141 .macro write_bpiall 142 /* Invalidate entire branch predictor array (register ignored) */ 143 mcr p15, 0, r0, c7, c5, 6 144 .endm 145 146 .macro write_dcimvac reg 147 /* Data cache invalidate by MVA */ 148 mcr p15, 0, \reg, c7, c6, 1 149 .endm 150 151 .macro write_dcisw reg 152 /* Data cache invalidate by set/way */ 153 mcr p15, 0, \reg, c7, c6, 2 154 .endm 155 156 .macro write_dccmvac reg 157 /* Data cache clean by MVA */ 158 mcr p15, 0, \reg, c7, c10, 1 159 .endm 160 161 .macro write_dccsw reg 162 /* Data cache clean by set/way */ 163 mcr p15, 0, \reg, c7, c10, 2 164 .endm 165 166 .macro write_dccimvac reg 167 /* Data cache invalidate by MVA */ 168 mcr p15, 0, \reg, c7, c14, 1 169 .endm 170 171 .macro write_dccisw reg 172 /* Data cache clean and invalidate by set/way */ 173 mcr p15, 0, \reg, c7, c14, 2 174 .endm 175 176 .macro write_tlbiall 177 /* Invalidate entire unified TLB (register ignored) */ 178 mcr p15, 0, r0, c8, c7, 0 179 .endm 180 181 .macro write_tlbiallis 182 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 183 mcr p15, 0, r0, c8, c3, 0 184 .endm 185 186 .macro write_tlbiasidis reg 187 /* Invalidate unified TLB by ASID Inner Sharable */ 188 mcr p15, 0, \reg, c8, c3, 2 189 .endm 190 191 .macro write_tlbimvaais reg 192 /* Invalidate unified TLB by MVA all ASID Inner Sharable */ 193 mcr p15, 0, \reg, c8, c3, 3 194 .endm 195 196 .macro write_prrr reg 197 mcr p15, 0, \reg, c10, c2, 0 198 .endm 199 200 .macro read_prrr reg 201 mrc p15, 0, \reg, c10, c2, 0 202 .endm 203 204 .macro write_nmrr reg 205 mcr p15, 0, \reg, c10, c2, 1 206 .endm 207 208 .macro read_nmrr reg 209 mrc p15, 0, \reg, c10, c2, 1 210 .endm 211 212 .macro read_vbar reg 213 mrc p15, 0, \reg, c12, c0, 0 214 .endm 215 216 .macro write_vbar reg 217 mcr p15, 0, \reg, c12, c0, 0 218 .endm 219 220 .macro write_mvbar reg 221 mcr p15, 0, \reg, c12, c0, 1 222 .endm 223 224 .macro read_mvbar reg 225 mrc p15, 0, \reg, c12, c0, 1 226 .endm 227 228 .macro write_fcseidr reg 229 mcr p15, 0, \reg, c13, c0, 0 230 .endm 231 232 .macro read_fcseidr reg 233 mrc p15, 0, \reg, c13, c0, 0 234 .endm 235 236 .macro write_contextidr reg 237 mcr p15, 0, \reg, c13, c0, 1 238 .endm 239 240 .macro read_contextidr reg 241 mrc p15, 0, \reg, c13, c0, 1 242 .endm 243 244 .macro write_tpidruro reg 245 mcr p15, 0, \reg, c13, c0, 3 246 .endm 247 248 .macro read_tpidruro reg 249 mrc p15, 0, \reg, c13, c0, 3 250 .endm 251 252 .macro read_clidr reg 253 /* Cache Level ID Register */ 254 mrc p15, 1, \reg, c0, c0, 1 255 .endm 256 257 .macro read_ccsidr reg 258 /* Cache Size ID Registers */ 259 mrc p15, 1, \reg, c0, c0, 0 260 .endm 261 262 .macro write_csselr reg 263 /* Cache Size Selection Register */ 264 mcr p15, 2, \reg, c0, c0, 0 265 .endm 266 267 .macro mov_imm reg, val 268 .if ((\val) & 0xffff0000) == 0 269 mov \reg, #(\val) 270 .else 271 movw \reg, #((\val) & 0xffff) 272 movt \reg, #((\val) >> 16) 273 .endif 274 .endm 275 276