1/* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Please keep them sorted based on the CRn register */ 29 .macro read_mpidr reg 30 mrc p15, 0, \reg, c0, c0, 5 31 .endm 32 33 .macro read_sctlr reg 34 mrc p15, 0, \reg, c1, c0, 0 35 .endm 36 37 .macro write_sctlr reg 38 mcr p15, 0, \reg, c1, c0, 0 39 .endm 40 41 .macro write_actlr reg 42 mcr p15, 0, \reg, c1, c0, 1 43 .endm 44 45 .macro write_cpacr reg 46 mcr p15, 0, \reg, c1, c0, 2 47 .endm 48 49 .macro read_cpacr reg 50 mrc p15, 0, \reg, c1, c0, 2 51 .endm 52 53 .macro read_scr reg 54 mrc p15, 0, \reg, c1, c1, 0 55 .endm 56 57 .macro write_scr reg 58 mcr p15, 0, \reg, c1, c1, 0 59 .endm 60 61 .macro write_nsacr reg 62 mcr p15, 0, \reg, c1, c1, 2 63 .endm 64 65 .macro write_ttbr0 reg 66 mcr p15, 0, \reg, c2, c0, 0 67 .endm 68 69 .macro read_ttbr0 reg 70 mrc p15, 0, \reg, c2, c0, 0 71 .endm 72 73 .macro write_ttbr1 reg 74 mcr p15, 0, \reg, c2, c0, 1 75 .endm 76 77 .macro read_ttbr1 reg 78 mrc p15, 0, \reg, c2, c0, 1 79 .endm 80 81 .macro write_ttbcr reg 82 mcr p15, 0, \reg, c2, c0, 2 83 .endm 84 85 .macro read_ttbcr reg 86 mrc p15, 0, \reg, c2, c0, 2 87 .endm 88 89 90 .macro write_dacr reg 91 mcr p15, 0, \reg, c3, c0, 0 92 .endm 93 94 .macro read_dacr reg 95 mrc p15, 0, \reg, c3, c0, 0 96 .endm 97 98 .macro read_dfsr reg 99 mrc p15, 0, \reg, c5, c0, 0 100 .endm 101 102 .macro write_iciallu 103 /* Invalidate all instruction caches to PoU (register ignored) */ 104 mcr p15, 0, r0, c7, c5, 0 105 .endm 106 107 .macro write_icialluis 108 /* 109 * Invalidate all instruction caches to PoU, Inner Shareable 110 * (register ignored) 111 */ 112 mcr p15, 0, r0, c7, c1, 0 113 .endm 114 115 .macro write_bpiall 116 /* Invalidate entire branch predictor array (register ignored) */ 117 mcr p15, 0, r0, c7, c5, 0 118 .endm 119 120 .macro write_bpiallis 121 /* 122 * Invalidate entire branch predictor array, Inner Shareable 123 * (register ignored) 124 */ 125 mcr p15, 0, r0, c7, c1, 6 126 .endm 127 128 .macro write_tlbiall 129 /* Invalidate entire unified TLB (register ignored) */ 130 mcr p15, 0, r0, c8, c7, 0 131 .endm 132 133 .macro write_tlbiallis 134 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 135 mcr p15, 0, r0, c8, c3, 0 136 .endm 137 138 .macro write_tlbiasidis reg 139 /* Invalidate unified TLB by ASID Inner Sharable */ 140 mcr p15, 0, \reg, c8, c3, 2 141 .endm 142 143 .macro write_prrr reg 144 mcr p15, 0, \reg, c10, c2, 0 145 .endm 146 147 .macro read_prrr reg 148 mrc p15, 0, \reg, c10, c2, 0 149 .endm 150 151 .macro write_nmrr reg 152 mcr p15, 0, \reg, c10, c2, 1 153 .endm 154 155 .macro read_nmrr reg 156 mrc p15, 0, \reg, c10, c2, 1 157 .endm 158 159 .macro read_vbar reg 160 mrc p15, 0, \reg, c12, c0, 0 161 .endm 162 163 .macro write_vbar reg 164 mcr p15, 0, \reg, c12, c0, 0 165 .endm 166 167 .macro write_mvbar reg 168 mcr p15, 0, \reg, c12, c0, 1 169 .endm 170 171 .macro read_mvbar reg 172 mrc p15, 0, \reg, c12, c0, 1 173 .endm 174 175 .macro write_fcseidr reg 176 mcr p15, 0, \reg, c13, c0, 0 177 .endm 178 179 .macro read_fcseidr reg 180 mrc p15, 0, \reg, c13, c0, 0 181 .endm 182 183 .macro write_contextidr reg 184 mcr p15, 0, \reg, c13, c0, 1 185 .endm 186 187 .macro read_contextidr reg 188 mrc p15, 0, \reg, c13, c0, 1 189 .endm 190 191 .macro write_tpidruro reg 192 mcr p15, 0, \reg, c13, c0, 3 193 .endm 194 195 .macro read_tpidruro reg 196 mrc p15, 0, \reg, c13, c0, 3 197 .endm 198 199 .macro read_actlr reg 200 mrc p15, 0, \reg, c1, c0, 1 201 .endm 202 203 .macro read_nsacr reg 204 mrc p15, 0, \reg, c1, c1, 2 205 .endm 206 207 .macro mov_imm reg, val 208 .if ((\val) & 0xffff0000) == 0 209 mov \reg, #(\val) 210 .else 211 movw \reg, #((\val) & 0xffff) 212 movt \reg, #((\val) >> 16) 213 .endif 214 .endm 215 216