| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 3672 MS_U16 u16bank_offset; in Hal_HDCP_clearflag() local
3677 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in Hal_HDCP_clearflag()
3678 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in Hal_HDCP_clearflag()
3679 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in Hal_HDCP_clearflag()
3680 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in Hal_HDCP_clearflag()
3682 HDCP_W2BYTE(REG_HDCP_DUAL_P0_01_L+u16bank_offset, 0xFF00 ); in Hal_HDCP_clearflag()
3691 MS_U16 u16hdcp_status, u16bank_offset; in Hal_HDCP_getstatus() local
3696 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in Hal_HDCP_getstatus()
3697 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in Hal_HDCP_getstatus()
3698 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in Hal_HDCP_getstatus()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 3716 MS_U16 u16bank_offset; in Hal_HDCP_clearflag() local
3726 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x151C00 in Hal_HDCP_clearflag()
3727 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x151F00 in Hal_HDCP_clearflag()
3728 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x152200 in Hal_HDCP_clearflag()
3729 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x152500 in Hal_HDCP_clearflag()
3731 HDCP_W2BYTE(REG_HDCP_DUAL_P0_01_L+u16bank_offset, 0xFF00 ); in Hal_HDCP_clearflag()
3740 MS_U16 u16hdcp_status, u16bank_offset; in Hal_HDCP_getstatus() local
3750 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x151C00 in Hal_HDCP_getstatus()
3751 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x151F00 in Hal_HDCP_getstatus()
3752 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x152200 in Hal_HDCP_getstatus()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 3716 MS_U16 u16bank_offset; in Hal_HDCP_clearflag() local
3726 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x151C00 in Hal_HDCP_clearflag()
3727 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x151F00 in Hal_HDCP_clearflag()
3728 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x152200 in Hal_HDCP_clearflag()
3729 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x152500 in Hal_HDCP_clearflag()
3731 HDCP_W2BYTE(REG_HDCP_DUAL_P0_01_L+u16bank_offset, 0xFF00 ); in Hal_HDCP_clearflag()
3740 MS_U16 u16hdcp_status, u16bank_offset; in Hal_HDCP_getstatus() local
3750 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x151C00 in Hal_HDCP_getstatus()
3751 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x151F00 in Hal_HDCP_getstatus()
3752 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x152200 in Hal_HDCP_getstatus()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 3861 MS_U16 u16bank_offset; in Hal_HDCP_clearflag() local
3866 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in Hal_HDCP_clearflag()
3867 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in Hal_HDCP_clearflag()
3868 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in Hal_HDCP_clearflag()
3869 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in Hal_HDCP_clearflag()
3871 HDCP_W2BYTE(REG_HDCP_DUAL_P0_01_L+u16bank_offset, 0xFF00 ); in Hal_HDCP_clearflag()
3880 MS_U16 u16hdcp_status, u16bank_offset; in Hal_HDCP_getstatus() local
3885 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in Hal_HDCP_getstatus()
3886 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in Hal_HDCP_getstatus()
3887 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in Hal_HDCP_getstatus()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 3861 MS_U16 u16bank_offset; in Hal_HDCP_clearflag() local
3866 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in Hal_HDCP_clearflag()
3867 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in Hal_HDCP_clearflag()
3868 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in Hal_HDCP_clearflag()
3869 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in Hal_HDCP_clearflag()
3871 HDCP_W2BYTE(REG_HDCP_DUAL_P0_01_L+u16bank_offset, 0xFF00 ); in Hal_HDCP_clearflag()
3880 MS_U16 u16hdcp_status, u16bank_offset; in Hal_HDCP_getstatus() local
3885 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in Hal_HDCP_getstatus()
3886 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in Hal_HDCP_getstatus()
3887 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in Hal_HDCP_getstatus()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 3655 MS_U16 u16bank_offset; in Hal_HDCP_clearflag() local
3660 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in Hal_HDCP_clearflag()
3661 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in Hal_HDCP_clearflag()
3662 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in Hal_HDCP_clearflag()
3663 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in Hal_HDCP_clearflag()
3665 HDCP_W2BYTE(REG_HDCP_DUAL_P0_01_L+u16bank_offset, 0xFF00 ); in Hal_HDCP_clearflag()
3674 MS_U16 u16hdcp_status, u16bank_offset; in Hal_HDCP_getstatus() local
3679 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in Hal_HDCP_getstatus()
3680 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in Hal_HDCP_getstatus()
3681 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in Hal_HDCP_getstatus()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 3855 MS_U16 u16bank_offset = 0; in _Hal_tmds_HDCPWriteX74() local
3862 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171000 in _Hal_tmds_HDCPWriteX74()
3863 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171300 in _Hal_tmds_HDCPWriteX74()
3864 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171600 in _Hal_tmds_HDCPWriteX74()
3865 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171900 in _Hal_tmds_HDCPWriteX74()
3872 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3873 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3875 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3876 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3880 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 3858 MS_U16 u16bank_offset = 0; in _Hal_tmds_HDCPWriteX74() local
3865 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171000 in _Hal_tmds_HDCPWriteX74()
3866 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171300 in _Hal_tmds_HDCPWriteX74()
3867 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171600 in _Hal_tmds_HDCPWriteX74()
3868 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171900 in _Hal_tmds_HDCPWriteX74()
3875 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3876 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3878 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3879 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3883 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 3858 MS_U16 u16bank_offset = 0; in _Hal_tmds_HDCPWriteX74() local
3865 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171000 in _Hal_tmds_HDCPWriteX74()
3866 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171300 in _Hal_tmds_HDCPWriteX74()
3867 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171600 in _Hal_tmds_HDCPWriteX74()
3868 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171900 in _Hal_tmds_HDCPWriteX74()
3875 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3876 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3878 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3879 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3883 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 3326 MS_U16 u16bank_offset = 0; in _Hal_tmds_HDCPWriteX74() local
3331 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3332 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3334 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3335 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3339 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
3340 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3343 while(R2BYTE(REG_HDCP_DUAL_P0_19_L +u16bank_offset) & BIT(7)); // wait write ready in _Hal_tmds_HDCPWriteX74()
3346 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3779 MS_U16 u16bank_offset = 0; in Hal_HDCP_clearflag() local
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 3326 MS_U16 u16bank_offset = 0; in _Hal_tmds_HDCPWriteX74() local
3331 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3332 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3334 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3335 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3339 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
3340 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3343 while(R2BYTE(REG_HDCP_DUAL_P0_19_L +u16bank_offset) & BIT(7)); // wait write ready in _Hal_tmds_HDCPWriteX74()
3346 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3779 MS_U16 u16bank_offset = 0; in Hal_HDCP_clearflag() local
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_hdmi.c | 714 MS_U16 u16bank_offset; in Hal_HDCP_clearflag() local
719 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x110A60 in Hal_HDCP_clearflag()
720 case INPUT_PORT_DVI1: u16bank_offset = 0x2900; break; // BK 0x113360 in Hal_HDCP_clearflag()
721 case INPUT_PORT_DVI3: u16bank_offset = 0x2B00; break; // BK 0x113560 in Hal_HDCP_clearflag()
722 case INPUT_PORT_DVI2: u16bank_offset = 0x2D00; break; // BK 0x113760 in Hal_HDCP_clearflag()
724 HDCP_W2BYTE(REG_HDCP_01_L+u16bank_offset, 0xFF00 ); in Hal_HDCP_clearflag()
733 MS_U16 u16hdcp_status, u16bank_offset; in Hal_HDCP_getstatus() local
738 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x110A60 in Hal_HDCP_getstatus()
739 case INPUT_PORT_DVI1: u16bank_offset = 0x2900; break; // BK 0x113360 in Hal_HDCP_getstatus()
740 case INPUT_PORT_DVI3: u16bank_offset = 0x2B00; break; // BK 0x113560 in Hal_HDCP_getstatus()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_hdmi.c | 714 MS_U16 u16bank_offset; in Hal_HDCP_clearflag() local
719 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x110A60 in Hal_HDCP_clearflag()
720 case INPUT_PORT_DVI1: u16bank_offset = 0x2900; break; // BK 0x113360 in Hal_HDCP_clearflag()
721 case INPUT_PORT_DVI3: u16bank_offset = 0x2B00; break; // BK 0x113560 in Hal_HDCP_clearflag()
722 case INPUT_PORT_DVI2: u16bank_offset = 0x2D00; break; // BK 0x113760 in Hal_HDCP_clearflag()
724 HDCP_W2BYTE(REG_HDCP_01_L+u16bank_offset, 0xFF00 ); in Hal_HDCP_clearflag()
733 MS_U16 u16hdcp_status, u16bank_offset; in Hal_HDCP_getstatus() local
738 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x110A60 in Hal_HDCP_getstatus()
739 case INPUT_PORT_DVI1: u16bank_offset = 0x2900; break; // BK 0x113360 in Hal_HDCP_getstatus()
740 case INPUT_PORT_DVI3: u16bank_offset = 0x2B00; break; // BK 0x113560 in Hal_HDCP_getstatus()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 1984 MS_U16 u16bank_offset = 0; in _Hal_tmds_HDCPWriteX74() local
1991 case INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171000 in _Hal_tmds_HDCPWriteX74()
1992 case INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171300 in _Hal_tmds_HDCPWriteX74()
1993 case INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171600 in _Hal_tmds_HDCPWriteX74()
1994 case INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171900 in _Hal_tmds_HDCPWriteX74()
2001 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
2002 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
2004 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
2005 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
2009 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/security/hal/maxim/aesdma/ |
| H A D | halAESDMA.c | 1255 MS_U16 u16bank_offset; in HAL_AESDMA_HDMI_GetM0() local
1263 case E_AESDMA_HDMI_INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in HAL_AESDMA_HDMI_GetM0()
1264 case E_AESDMA_HDMI_INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in HAL_AESDMA_HDMI_GetM0()
1265 case E_AESDMA_HDMI_INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in HAL_AESDMA_HDMI_GetM0()
1266 case E_AESDMA_HDMI_INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in HAL_AESDMA_HDMI_GetM0()
1272 …m0[i] = _AESDMA_REG32_R(&((REG_HDCP14SEKCtrl*)((MS_U16*)_HDCP14SekCtrl + u16bank_offset))[i].REG_0… in HAL_AESDMA_HDMI_GetM0()
|
| /utopia/UTPA2-700.0.x/modules/security/hal/manhattan/aesdma/ |
| H A D | halAESDMA.c | 1277 MS_U16 u16bank_offset; in HAL_AESDMA_HDMI_GetM0() local
1285 case E_AESDMA_HDMI_INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in HAL_AESDMA_HDMI_GetM0()
1286 case E_AESDMA_HDMI_INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in HAL_AESDMA_HDMI_GetM0()
1287 case E_AESDMA_HDMI_INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in HAL_AESDMA_HDMI_GetM0()
1288 case E_AESDMA_HDMI_INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in HAL_AESDMA_HDMI_GetM0()
1294 …m0[i] = _AESDMA_REG32_R(&((REG_HDCP14SEKCtrl*)((MS_U16*)_HDCP14SekCtrl + u16bank_offset))[i].REG_0… in HAL_AESDMA_HDMI_GetM0()
|
| /utopia/UTPA2-700.0.x/modules/security/hal/M7621/aesdma/ |
| H A D | halAESDMA.c | 1255 MS_U16 u16bank_offset; in HAL_AESDMA_HDMI_GetM0() local
1263 case E_AESDMA_HDMI_INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in HAL_AESDMA_HDMI_GetM0()
1264 case E_AESDMA_HDMI_INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in HAL_AESDMA_HDMI_GetM0()
1265 case E_AESDMA_HDMI_INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in HAL_AESDMA_HDMI_GetM0()
1266 case E_AESDMA_HDMI_INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in HAL_AESDMA_HDMI_GetM0()
1272 …m0[i] = _AESDMA_REG32_R(&((REG_HDCP14SEKCtrl*)((MS_U16*)_HDCP14SekCtrl + u16bank_offset))[i].REG_0… in HAL_AESDMA_HDMI_GetM0()
|
| /utopia/UTPA2-700.0.x/modules/security/hal/maserati/aesdma/ |
| H A D | halAESDMA.c | 1312 MS_U16 u16bank_offset; in HAL_AESDMA_HDMI_GetM0() local
1320 case E_AESDMA_HDMI_INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in HAL_AESDMA_HDMI_GetM0()
1321 case E_AESDMA_HDMI_INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in HAL_AESDMA_HDMI_GetM0()
1322 case E_AESDMA_HDMI_INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in HAL_AESDMA_HDMI_GetM0()
1323 case E_AESDMA_HDMI_INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in HAL_AESDMA_HDMI_GetM0()
1329 …m0[i] = _AESDMA_REG32_R(&((REG_HDCP14SEKCtrl*)((MS_U16*)_HDCP14SekCtrl + u16bank_offset))[i].REG_0… in HAL_AESDMA_HDMI_GetM0()
|
| /utopia/UTPA2-700.0.x/modules/security/hal/M7821/aesdma/ |
| H A D | halAESDMA.c | 1312 MS_U16 u16bank_offset; in HAL_AESDMA_HDMI_GetM0() local
1320 case E_AESDMA_HDMI_INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200 in HAL_AESDMA_HDMI_GetM0()
1321 case E_AESDMA_HDMI_INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500 in HAL_AESDMA_HDMI_GetM0()
1322 case E_AESDMA_HDMI_INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800 in HAL_AESDMA_HDMI_GetM0()
1323 case E_AESDMA_HDMI_INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00 in HAL_AESDMA_HDMI_GetM0()
1329 …m0[i] = _AESDMA_REG32_R(&((REG_HDCP14SEKCtrl*)((MS_U16*)_HDCP14SekCtrl + u16bank_offset))[i].REG_0… in HAL_AESDMA_HDMI_GetM0()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 2860 MS_U16 u16bank_offset =0; in Hal_DVI_IMMESWITCH_PS_SW_Path()
2866 case 0: u16bank_offset = 0x0000; u8reg_offset = 0x00; break; in Hal_DVI_IMMESWITCH_PS_SW_Path()
2867 case 1: u16bank_offset = 0x2900; u8reg_offset = 0x40; break; in Hal_DVI_IMMESWITCH_PS_SW_Path()
2868 case 2: u16bank_offset = 0x2B00; u8reg_offset = 0x80; break; in Hal_DVI_IMMESWITCH_PS_SW_Path()
2869 case 3: u16bank_offset = 0x2D00; u8reg_offset = 0xC0; break; in Hal_DVI_IMMESWITCH_PS_SW_Path()
2874 …if( (R2BYTE(REG_DVI_DTOP_16_L+u16bank_offset) & BIT(10)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offs… in Hal_DVI_IMMESWITCH_PS_SW_Path()
2882 …REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) & BIT(6)) && … in Hal_DVI_IMMESWITCH_PS_SW_Path()
|