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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h134 #define CHIP_ALLPAD_IN (__BIT7)
151 #define CHIP_REG_HWI2C_MIIC1_CLL_36M (__BIT7)
152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7)
153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
176 #define _MIIC_CFG_RESERVED (__BIT7)
221 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
259 #define _MIIC_CFG_RESERVED (__BIT7)
304 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h134 #define CHIP_ALLPAD_IN (__BIT7)
151 #define CHIP_REG_HWI2C_MIIC1_CLL_36M (__BIT7)
152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7)
153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
176 #define _MIIC_CFG_RESERVED (__BIT7)
221 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
259 #define _MIIC_CFG_RESERVED (__BIT7)
304 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h134 #define CHIP_ALLPAD_IN (__BIT7)
151 #define CHIP_REG_HWI2C_MIIC1_CLL_36M (__BIT7)
152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7)
153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
176 #define _MIIC_CFG_RESERVED (__BIT7)
221 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
259 #define _MIIC_CFG_RESERVED (__BIT7)
304 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h134 #define CHIP_ALLPAD_IN (__BIT7)
151 #define CHIP_REG_HWI2C_MIIC1_CLL_36M (__BIT7)
152 #define CHIP_REG_HWI2C_MIIC1_CLK_54M (__BIT6 | __BIT7)
153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
176 #define _MIIC_CFG_RESERVED (__BIT7)
221 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
259 #define _MIIC_CFG_RESERVED (__BIT7)
304 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DregHWI2C.h136 #define CHIP_MIIC3_PAD_1 (__BIT7)
137 #define CHIP_MIIC3_PAD_MSK (__BIT7)
153 #define CHIP_ALLPAD_IN (__BIT7)
171 #define _MIIC_CFG_RESERVED (__BIT7)
217 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DregHWI2C.h136 #define CHIP_MIIC3_PAD_1 (__BIT7)
137 #define CHIP_MIIC3_PAD_MSK (__BIT7)
153 #define CHIP_ALLPAD_IN (__BIT7)
171 #define _MIIC_CFG_RESERVED (__BIT7)
217 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h155 #define CHIP_ALLPAD_IN (__BIT7)
173 #define _MIIC_CFG_RESERVED (__BIT7)
237 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
248 #define _DMA_CMDDAT7_MSK (__BIT7)//SDA delay 2T
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h155 #define CHIP_ALLPAD_IN (__BIT7)
173 #define _MIIC_CFG_RESERVED (__BIT7)
237 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
248 #define _DMA_CMDDAT7_MSK (__BIT7)//SDA delay 2T
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h155 #define CHIP_ALLPAD_IN (__BIT7)
173 #define _MIIC_CFG_RESERVED (__BIT7)
237 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
248 #define _DMA_CMDDAT7_MSK (__BIT7)//SDA delay 2T
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h155 #define CHIP_ALLPAD_IN (__BIT7)
173 #define _MIIC_CFG_RESERVED (__BIT7)
237 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
248 #define _DMA_CMDDAT7_MSK (__BIT7)//SDA delay 2T
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h155 #define CHIP_ALLPAD_IN (__BIT7)
173 #define _MIIC_CFG_RESERVED (__BIT7)
237 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
248 #define _DMA_CMDDAT7_MSK (__BIT7)//SDA delay 2T
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregEMMflt.h113 #define __BIT7 __BIT(7) macro
169 #define EMM_RESET_INT __BIT7
257 #define REG_LPCR1_WLD __BIT7
273 #define REG_DATA_CHK_2T __BIT7
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DregEMMflt.h113 #define __BIT7 __BIT(7) macro
169 #define EMM_RESET_INT __BIT7
257 #define REG_LPCR1_WLD __BIT7
273 #define REG_DATA_CHK_2T __BIT7
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregEMMflt.h113 #define __BIT7 __BIT(7) macro
169 #define EMM_RESET_INT __BIT7
257 #define REG_LPCR1_WLD __BIT7
273 #define REG_DATA_CHK_2T __BIT7
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregEMMflt.h113 #define __BIT7 __BIT(7) macro
169 #define EMM_RESET_INT __BIT7
257 #define REG_LPCR1_WLD __BIT7
273 #define REG_DATA_CHK_2T __BIT7
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregEMMflt.h113 #define __BIT7 __BIT(7) macro
169 #define EMM_RESET_INT __BIT7
257 #define REG_LPCR1_WLD __BIT7
273 #define REG_DATA_CHK_2T __BIT7
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DregHWI2C.h133 #define CHIP_ALLPAD_IN (__BIT7)
151 #define _MIIC_CFG_RESERVED (__BIT7)
197 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DregHWI2C.h155 #define CHIP_ALLPAD_IN (__BIT7)
173 #define _MIIC_CFG_RESERVED (__BIT7)
219 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/ir_tx/hal/k6lite/ir_tx/
H A Dreg_IR_TX.h9 #define __BIT7 __BIT(7UL) macro
114 #define IR_TX_Unit03_L __BIT7
131 #define IR_TX_Unit11_L __BIT7
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DregHWI2C.h155 #define CHIP_ALLPAD_IN (__BIT7)
173 #define _MIIC_CFG_RESERVED (__BIT7)
219 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DregHWI2C.h155 #define CHIP_ALLPAD_IN (__BIT7)
173 #define _MIIC_CFG_RESERVED (__BIT7)
219 #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1
/utopia/UTPA2-700.0.x/modules/pm/hal/maldives/pm/
H A DhalPM.c536 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
598 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
645 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetDRAMOffsetForMCU()
744 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/mustang/pm/
H A DhalPM.c536 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
598 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
645 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetDRAMOffsetForMCU()
744 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/mainz/pm/
H A DhalPM.c537 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
647 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetDRAMOffsetForMCU()
755 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/k6lite/pm/
H A DhalPM.c671 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
719 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
766 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetDRAMOffsetForMCU()
861 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)

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